Semiconductor integrated circuit device
AssigneesHitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
InventorsNorikatsu Takaura, Hideyuki Matsuoka, Motoyasu Terao, Kenzo Kurotsuchi, Tsuyoshi Yamauchi
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Abstract
With a high-speed nonvolatile phase change memory, reliability in respect of the number of refresh times is enhanced. In a memory cell forming area of a phase change memory using a MISFET as a transistor for selection of memory cells, a phase change material layer of a memory cell comprising a resistor element, using a phase change material, is formed for common use. As a result, variation in shape and a change in composition of the phase change material, caused by isolation of memory cell elements by etching, are reduced, thereby enhancing reliability of memory cells, in respect of the number of refresh times.
Claims16
A semiconductor integrated circuit device having a plurality of memory cells formed on a semiconductor substrate, each made up by electrically connecting a resistor element in series with a field effect transistor comprising:
- a plurality of first electrodes each connected to the field effect transistor which is included in a corresponding one of the plurality of memory cells;
- a stacked layer film formed of a phase change material layer and a second electrode, deposited in that order, and connected to the plurality of first electrodes in common;
- and
- a power source terminal connected to the second electrode layer,
- wherein the phase change material layer is made of one phase change material layer or plural phase change material layers with resistance values changing by heating treatments,
- wherein the resistor element is a part of the stacked layer film,
- wherein a surface area of each of the plurality of first electrodes is smaller than a surface area of the stacked layer film, and
- wherein a phase change region is formed in a contact part between one of the plurality of first electrodes and the stacked layer.
A semiconductor integrated circuit device comprising a plurality of memory cells formed on a semiconductor substrate, each made up by electrically connecting a resistor element in series with a field effect transistor comprising:
- a plurality of first electrodes each connected to either of a source or a drain of the field effect transistor which is included in a corresponding one of the plurality of memory cells;
- a conductive film serving as a bit line of the memory cells and connected to the other of the source or the drain of the field effect transistor;
- and
- a stacked layer film made up of a phase change material layer and a second electrode layer, deposited in that order,
- wherein the phase change material layer is made of one phase change material layer or plural phase chanae material layers with resistance values changing by heating treatments,
- wherein the stacked layer film is formed on the conductive film through the intermediary of an insulation film so as to be connected to the plurality of first electrodes in common,
- wherein the resistor element is a part of the stacked layer film,
- wherein a surface area of each of the plurality of first electrodes is smaller than a surface area of the stacked layer film, and
- wherein a phase change region is formed in a contact part between one of the plurality of first electrodes and the stacked layer.
A semiconductor integrated circuit device comprising a plurality of memory cells formed on a semiconductor substrate, each made up by electrically connecting a resistor element in series with a field effect transistor comprising:
- a plurality of first electrodes each connected to either of a source or a drain of the field effect transistor which is included in a corresponding one of the plurality of memory cells;
- a conductive film serving as a bit line of the memory cells and connected to the other of the source or the drain of the field effect transistor;
- and
- a stacked layer film made up of phase change material layer and a second electrode layer, deposited in that order,
- wherein the phase change material layer is made of one phase change material layer or plural phase change material layers with resistance values changing by heating treatments,
- wherein the stacked layer film is formed on the conductive film through the intermediary of an insulation film and configured such that the phase change material layers are divided by the memory cell and the second electrode layer is common to the plurality of memory cells,
- wherein the resistor element is a part of the stacked layer film,
- wherein a surface area of each of the plurality of first electrodes is smaller than a surface area of the stacked layer film, and
- wherein a phase change region is formed in a contact part between one of the plurality of first electrodes and the stacked layer.
Dependencies are inferred from the claim text.