Laser alignment target
AssigneeAltera Corporation
InventorRaminda U. Madurawe
Life of this patent
Estimating the term…
Abstract
A technique to form a structure with a rough topography in a planarized semiconductor process. The rough topography is formed by creating cored contacts. Subsequent process layers may be further stacked on top of the cored contacts in order to augment the nonplanar characteristics of the cored contacts. This rough topography structure may be used to align integrated circuits and wafers. An integrated circuit may be laser aligned using this alignment structure.
Claims28
A method of programming a laser programmable integrated circuit, comprising:
- providing an alignment structure on the integrated circuit, the alignment structure formed using a planarized process, the alignment structure comprising a substrate, a first region formed on the substrate, and a second region formed on the substrate adjacent to the first region, the first region characterized by a first optical reflectiveness value and the second region characterized by a second optical reflectiveness value different from the first optical reflectiveness value;
- aligning the integrated circuit using the alignment structure;
- referencing a first programmable element located on the integrated circuit using a laser;
- and
- programming the first programmable element using the laser.
A method of programming a laser programmable integrated circuit, comprising:
- providing an alignment structure on the integrated circuit, the alignment structure formed in a planarized semiconductor process, the alignment structure comprising:
- a substrate;
- a first region formed on the substrate, the first region characterized by a first optical reflectiveness value;
- and
- a second region formed on the substrate adjacent to the first region, the second region characterized by a second optical reflectiveness value different from the first optical reflectiveness value, the second region comprising:
- a first conductive layer;
- a second conductive layer;
- an first insulating layer, between the first and second conductive layers, wherein the first insulating layer has a first opening for electrically coupling the first and second conductive layers;
- and
- a plug layer filling the first opening, wherein the first plug layer has a cored region, whereby a topographical roughness formed by the cored region scatters incident radiation;
- aligning the integrated circuit using the alignment structure;
- referencing a first programmable element located on the integrated circuit using a laser;
- and
- programming the first programmable element using the laser.
A method of programming a programmable logic integrated circuit comprising:
- aligning the programmable logic integrated circuit, fabricated using a planarized process, using a laser to scan a plurality of alignment structures formed on the integrated circuit, wherein each alignment structure in the plurality of alignment structures comprises:
- a first region formed on a substrate of the integrated circuit, the first region characterized by a first optical reflectiveness value;
- and
- a second region formed on the substrate adjacent to the first region, the second region characterized by a second optical reflectiveness value different from the first optical reflectiveness value;
- and
- programming a first programmable element of the programmable logic integrated circuit using the laser.
Dependencies are inferred from the claim text.