# US 7,071,098 B2 · Methods of fabricating interconnects for semiconductor components including a through hole entirely through the component and forming a metal nitride including separate precursor cycles

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- Number: US 7,071,098 B2
- Document ID: US7071098B2
- Status: Granted
- Kind: B2
- Application number: 11/028,918
- Filed: 2005-01-03
- Published: 2005-08-25
- Granted: 2006-07-04
- Earliest claimed: 2004-02-20
- Assignees: Micron Technology, Inc.
- Inventors: Kyle K. Kirby; Shuang Meng; Garo J. Derderian
- Web page: https://patentgrep.com/patent/US7071098B2

## CPC

- C23C 16/34: Nitrides {(C23C16/303 takes precedence)}
- C23C 16/45525: {Atomic layer deposition [ALD]}
- C23C 18/1608: {from pretreatment step, i.e. selective pre-treatment}
- C23C 18/1879: {Use of metal, e.g. activation, sensitisation with noble metals}
- H10D 84/01: Manufacture or treatment
- H10P 14/432: {using selective deposition}
- H10P 14/46: using a liquid
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0238: {comprising etching via holes through pads or through electrodes}
- H10W 20/0249: {wherein the through-semiconductor via protrudes from backsides of the chips, wafers or substrates during the manufacture}
- H10W 20/0261: {characterised by the filling method or the material of the conductive fill}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- C23C 18/36: using hypophosphites
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 72/01904: {using temporary auxiliary members, e.g. using sacrificial coatings or handle substrates}
- H10W 72/221: {Structures or relative sizes}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/251: {Materials}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- C23C: COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL (making metal-coated products by extrusion B21C23/22; covering with metal by connecting pre-existing layers to articles, see the relevant places, e.g. B21D39/00, B23K; metallising of glass C03C; metallising mortars, concrete, artificial stone, ceramics or natural stone C04B41/00; enamelling of, or applying a vitreous layer to, metals C23D; treating metal surfaces or coating of metals by electrolysis or electrophoresis C25D; single-crystal film growth C30B; by metallising textiles D06M11/83; decorating textiles by locally metallising D06Q1/04)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

In one aspect, the invention encompasses a method of fabricating an interconnect for a semiconductor component. A semiconductor substrate is provided, and an opening is formed which extends entirely through the substrate. A first material is deposited along sidewalls of the opening at a temperature of less than or equal to about 200° C. The deposition can comprise one or both of atomic layer deposition and chemical vapor deposition, and the first material can comprise a metal nitride. A solder-wetting material is formed over a surface of the first material. The solder-wetting material can comprise, for example, nickel. Subsequently, solder is provided within the opening and over the solder-wetting material.

## Claims

### Claim 1

A method of fabricating an interconnect for a semiconductor component, comprising:
providing a semiconductor component;
forming an opening which extends entirely through the component, the opening having sidewalls;
depositing a metal nitride along the sidewalls of the opening, the depositing being conducted in a reaction chamber utilizing:
a first precursor containing the metal of the metal nitride;
a second precursor containing the nitrogen of the metal nitride; and
at least one cycle in which the first and second precursors are in the reaction chamber at different and substantially non-overlapping time intervals relative to one another; and
plating a second material within the opening and over the metal nitride.

### Claim 2 (depends on 1)

The method of claim 1 wherein the plating is electroless plating.

### Claim 3 (depends on 1)

The method of claim 1 wherein the component comprises a semiconductor material wafer.

### Claim 4 (depends on 1)

The method of claim 1 wherein the component comprises a monocrystalline silicon wafer.

### Claim 5 (depends on 1)

The method of claim 1 wherein the opening has a length through the component and a maximum dimension orthogonal to the length of less than or equal to about 100 microns.

### Claim 6 (depends on 1)

The method of claim 1 wherein a temperature of the component during the at least one cycle is less than or equal to about 200° C.

### Claim 7 (depends on 1)

The method of claim 1 wherein a temperature of the component during the at least one cycle is less than or equal to about 160° C.

### Claim 8 (depends on 1)

The method of claim 1 wherein the metal nitride is titanium nitride, tungsten nitride, tantalum nitride or hafnium nitride.

### Claim 9 (depends on 1)

The method of claim 1 wherein the metal nitride is titanium nitride.

### Claim 10 (depends on 9)

The method of claim 9 wherein the first precursor is TiCl4 and the second precursor is NH3.

### Claim 11 (depends on 9)

The method of claim 9 wherein the first precursor is TDMAT and the second precursor is NH3.

### Claim 12 (depends on 11)

The method of claim 11 wherein the cycle utilizes, in the following sequential order, a first pulse of the TDMAT into the reaction chamber, a substantial purge of the TDMAT from the reaction chamber, and a second pulse of the NH3 into the reaction chamber.

### Claim 13 (depends on 12)

The method of claim 12 wherein the first pulse is for a time of about 1 second, the purge is for a time of about 10 seconds and utilizes a purge gas which is inert relative to reaction with the TDMAT and the component, and the second pulse is for a time of about 4 seconds.

### Claim 14 (depends on 1)

The method of claim 1 wherein, during each of the at least one cycles, the first precursor is introduced into the reaction chamber before the second precursor.

### Claim 15 (depends on 1)

The method of claim 1 wherein each of the at least one cycles individually forms a layer of the metal nitride that is less than or equal to about 10 Å thick.

### Claim 16 (depends on 15)

The method of claim 15 wherein enough of the cycles are utilized so that the depositing forms the metal nitride to be at least about 100 Å thick.

### Claim 17 (depends on 15)

The method of claim 15 wherein enough of the cycles are utilized so that the depositing forms the metal nitride to be from about 100 Å thick to about 300 Å thick.

### Claim 18 (depends on 1)

The method of claim 1 wherein the second material is a solder-wetting material, and further comprising forming solder within the opening and along the second material.

### Claim 19 (depends on 18)

The method of claim 18 wherein the second material comprises nickel.