# US 7,071,097 B2 · Method for improved process latitude by elongated via integration

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- Number: US 7,071,097 B2
- Document ID: US7071097B2
- Status: Granted
- Kind: B2
- Application number: 10/887,086
- Filed: 2004-07-09
- Published: 2006-01-12
- Granted: 2006-07-04
- Earliest claimed: 2004-07-09
- Assignees: International Business Machines Corporation
- Inventors: Matthew E. Colburn
- Web page: https://patentgrep.com/patent/US7071097B2

## CPC

- H10W 20/071: {of dielectric parts thereof}
- H10W 20/074: {of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers}
- H10W 20/084: {for dual-damascene structures}
- H10W 20/086: {involving buried masks}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Interconnect dual damascene structure are fabricated by depositing on a layer of at least one dielectric, a mask forming layer for providing the via-level mask layer of the dual damascene structures; creating an elongated via pattern in the via-level mask layer; depositing a layer of line-level dielectric and creating a line pattern through the layer of line-level dielectric, and transferring the line pattern through the projected intersection of the elongated via-level pattern and of the line-level pattern thereby generating an aligned dual damascene structure. A conductive liner layer is deposited in the dual damascene structure followed by filling the dual damascene structure with a conductive fill metal to form a set of metal lines. The metal and liner layers are planarized.

## Claims

### Claim 1

A method for fabricating an interconnect dual damascene structure which comprises:
a) providing a layer of at least one dielectric on a substrate surface;
b) depositing on the layer of the at least one dielectric, a mask forming layer for providing a via-level mask layer;
c) creating an elongated via pattern in the via-level mask layer; wherein said elongated via pattern is elongated in the orthogonal direction to a subsequently to be formed line level pattern;
d) depositing a layer of line-level dielectric;
e) creating a line pattern through the layer of line-level dielectric;
f) transferring the line pattern through the projected intersection of the elongated via-level pattern and of the line-level pattern to generate an aligned dual damascene structure, which is self aligned in said orthogonal direction;
g) depositing a conductive liner layer and then filling the dual damascene structure with a conductive fill metal to form a set of metal lines; and
h) planarizing the metal and liner layers so that the metal is coplanar with the top of layer of at least one dielectric on the substrate surface.

### Claim 2 (depends on 1)

The method of claim 1, wherein the mask-forming layers are hardmask materials.

### Claim 3 (depends on 1)

The method of claim 1, wherein the elongated via pattern is elongated by at least 10% of the line-to-line spacing.

### Claim 4 (depends on 1)

The method of claim 1, wherein the elongated via pattern is elongated by less than ½ the line-to-line spacing.

### Claim 5 (depends on 1)

The method of claim 1, wherein the elongated via pattern is elongated from about 10% to less than ½ the line-to-line spacing.

### Claim 6 (depends on 1)

The method of claim 1, wherein the conductive fill material comprises Cu or Ag alloy.

### Claim 7 (depends on 1)

The method of claim 1, wherein the planarizing comprises chemical-mechanical polishing.

### Claim 8 (depends on 1)

The method of claim 1, wherein the barrier material comprises tungsten.

### Claim 9 (depends on 1)

An interconnect structure obtained by the process of claim 1.