# US 7,071,092 B2 · Method of manufacturing antenna proximity lines

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- Number: US 7,071,092 B2
- Document ID: US7071092B2
- Status: Granted
- Kind: B2
- Application number: 11/042,669
- Filed: 2005-01-25
- Published: 2005-06-23
- Granted: 2006-07-04
- Earliest claimed: 2003-03-21
- Assignees: Texas Instruments Incorporated
- Inventors: Anand T. Krishnan; Srikanth Krishnan
- Web page: https://patentgrep.com/patent/US7071092B2

## CPC

- H10W 72/00: Interconnections or connectors in packages
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An embodiment of the invention is an integrated circuit 2 having antenna proximity lines 3 coupled to the semiconductor substrate 5. Another embodiment of the invention is a method of manufacturing an integrated circuit 2 having antenna proximity lines 3 coupled to the semiconductor substrate 5.

## Claims

### Claim 1

A method of manufacturing an integrated circuit comprising:
forming a transistor level containing logic elements over a semiconductor substrate, said transistor level including semiconductor substrate contacts, said semiconductor substrate contacts having direct contact with said semiconductor substrate, said transistor level also including logic element contacts, said logic element contacts having direct contact with said logic elements;
forming a first dielectric layer over said transistor level;
etching said first dielectric layer to form voids for first level metal interconnects and first level antenna proximity lines; and
forming said first level metal interconnects and said first level antenna proximity lines, said first level antenna proximity lines being coupled to said semiconductor substrate contacts, and said first level metal interconnects being coupled to said logic element contacts.

### Claim 2 (depends on 1)

The method of claim 1 wherein said first level antenna proximity lines comprise copper.

### Claim 3 (depends on 1)

The method of claim 1 further comprising:
forming a second dielectric layer in direct contact with said first dielectric layer;
etching said second dielectric layer to form voids for second level metal interconnects and second level antenna proximity lines; and
forming said second level metal interconnects and said second level antenna proximity lines, said second level antenna proximity lines being coupled to said semiconductor substrate contacts, and said second level metal interconnects being coupled to said logic element contacts.

### Claim 4 (depends on 1)

The method of claim 1 wherein said first level antenna proximity lines are spaced less than 1.5 μm from an edge of said first level metal interconnects.

### Claim 5 (depends on 3)

The method of claim 3 wherein said second level antenna proximity lines are spaced less than 1.5 μm from an edge of said second level metal interconnects.

### Claim 6 (depends on 1)

The method of claim 1 further comprising:
forming a second dielectric layer in direct contact with said first dielectric layer;
etching said second dielectric layer to form voids for second level metal interconnects, second level antenna proximity lines, and vias; and
forming said second level metal interconnects, said second level antenna proximity lines, and vias; wherein said second level antenna proximity lines are coupled to said semiconductor substrate contacts and said second level metal interconnects are coupled to said logic element contacts.

### Claim 7 (depends on 6)

The method of claim 6 wherein said second level antenna proximity lines are spaced less than 1.5 μm from an edge of said second level metal interconnects.