# US 7,071,087 B2 · Technique to grow high quality ZnSe epitaxy layer on Si substrate

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- Number: US 7,071,087 B2
- Document ID: US7071087B2
- Status: Granted
- Kind: B2
- Application number: 10/859,764
- Filed: 2004-06-03
- Published: 2005-10-20
- Granted: 2006-07-04
- Earliest claimed: 2004-04-14
- Assignees: Witty Mate Corporation
- Inventors: Tsung-Hsi Yang; Chung-Liang Lee; Chu-Shou Yang; Guangli Luo; Wu-Ching Chou; Chun-Yen Chang; Tsung-Yeh Yang
- Web page: https://patentgrep.com/patent/US7071087B2

## CPC

- H10F 77/123: comprising only Group II-VI materials, e.g. CdS, ZnS or HgCdTe
- C30B 23/02: Epitaxial-layer growth
- C30B 29/48: AIIBVI compounds {wherein A is Zn, Cd or Hg, and B is S, Se or Te}
- C30B 29/52: Alloys
- H10H 20/0125: {with a substrate not being Group II-VI materials}
- H10P 14/22: using physical deposition, e.g. vacuum deposition or sputtering
- H10P 14/24: using chemical vapour deposition [CVD]
- H10P 14/2905: {Silicon, silicon germanium or germanium}
- H10P 14/3211: {Silicon, silicon germanium or germanium}
- H10P 14/3251: {consisting of three or more layers}
- H10P 14/3431: {Selenides}
- H10P 14/3436: {being chalcogenide semiconductor materials not being oxides, e.g. ternary compounds}
- H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- C30B: SINGLE-CRYSTAL GROWTH (by using ultra-high pressure, e.g. for the formation of diamonds, B01J3/06); UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL (zone-refining of metals or alloys C22B); PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE (casting of metals, casting of other substances by the same processes or devices B22D; working of plastics B29; modifying the physical structure of metals or alloys C21D, C22F); SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE (for producing semiconductor devices or parts thereof H10); APPARATUS THEREFOR
- H10H: INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A technique to grow high quality and large area ZnSe layer on Si substrate is provided, comprising growing GexSi1−x/Ge epitaxial layers on Si substrate by using ultra-high vacuum chemical vapor deposition (UHVCVD), and finally growing a ZnSe film on top Ge buffer layers. Two concepts are applied in the process of this invention, the first one is to block the dislocations generated from GexSi1−x epitaxial layers and to terminate the propagated upward dislocations by using strained interfaces, accordingly the dislocation density of ZnSe layer is greatly reduced and the surface roughness is improved; the second concept is to solve the problems of anti-phase domain due to growth of polar materials on non-polar material using off-cut angle Si substrate, and that is free from diffusion problems between different atoms while generally growing ZnSe layers on Si substrate.

## Claims

### Claim 1

A process to grow ZnSe film on Si substrate, comprising:
(1) providing a clean flat Si substrate;
(2) growing a first SiGe epitaxital layer with a given thickness to contain a large amount of threading dislocation created by lattice dislocation at the bottom of the layer and interfaces;
(3) performing high temperature annealing to the first SiGe epitaxital layer in situ to reduce threading dislocation density;
(4) growing a second and optionally a third SiGe epitaxital layer to terminate the threading dislocation propagating upward from the first epitaxital layer with the produced strained interfaces, and performing high temperature annealing in situ during both growing periods;
(5) growing a pure Ge layer on the surface of the top epitaxital layer obtained in step (4); and
(6) eventually growing a ZnSe layer on the pure Ge layer.

### Claim 2 (depends on 1)

The process of claim 1, wherein the growing in steps (2) to (5) are conducted by ultra-high vacuum chemical vapor deposition under growing gas pressure of 20 to 100 mTorr at 350 to 650° C., and the growing in step (6) is conducted by molecular beam epitaxy; further, the high temperature annealing treatment is performed in situ at 700˜750° C. for 0.25 to 0.5 hour.

### Claim 3 (depends on 1)

The process of claim 1, wherein the Si substrate in step (1) is cleaned by the standard cleaning procedure, is rinsed with 10 wt % hydrofluoric acid solution, and is prebaked at 800° C. for 10 minutes to remove oxide layer.

### Claim 4 (depends on 1)

The process of claim 1, wherein the first SiGe epitaxital layer is Si0.1Ge0.9 of at least 0.1 μm thick.

### Claim 5 (depends on 1)

The process of claim 1, wherein the first SiGe epitaxital layer is Si0.1Ge0.9 of 0.5 to 0.8 μm thick.

### Claim 6 (depends on 1)

The process of claim 1, wherein the second SiGe epitaxital layer is Si0.05Ge0.95 of at least 0.1 μm thick.

### Claim 7 (depends on 1)

The process of claim 1, wherein the second SiGe epitaxital layer is Si0.05Ge0.95 of 0.5 to 0.8 μm thick.

### Claim 8 (depends on 1)

The process of claim 1, wherein the optional third SiGe epitaxital layer is Si0.02Ge0.98 of at least 0.1 μm thick.

### Claim 9 (depends on 1)

The process of claim 1, wherein the optional third SiGe epitaxital layer is Si0.02Ge0.98 of 0.5 to 0.8 μm thick.

### Claim 10 (depends on 1)

The process of claim 1, wherein the Ge molar content of the first SiGe epitaxital layer is 70 to 90%.

### Claim 11 (depends on 1)

The process of claim 1, wherein the Ge molar content of the second SiGe epitaxital layer is 80 to 95%.

### Claim 12 (depends on 2)

The process of claim 2, wherein the epitaxy growing temperature is 400° C.

### Claim 13 (depends on 2)

The process of claim 2, wherein the high temperature annealing is performed in situ at 750° C. for at least 15 minutes.

### Claim 14 (depends on 2)

The process of claim 2, wherein the atmosphere used in the high temperature annealing in situ is hydrogen, and the annealing gas pressure is 20 mTorr.

### Claim 15

A ZnSe epitaxital semiconductor structure, comprising a Si substrate, a first SiGe epitaxital layer with Ge mole fraction of at least 70%, a second SiGe epitaxital layer with higher Ge mole fraction, and optionally a third SiGe epitaxital layer with Ge mole fraction higher than that of the second SiGe epitaxital layer, a pure Ge layer, and a ZnSe layer as the top layer, characterized in: the first SiGe epitaxital layer can, at the bottom of the layer and interfaces, contain a large amount of threading dislocation created by lattice dislocation, and the second SiGe epitaxital layer and the optional third SiGe epitaxital layer can, with the strained interfaces thereof, terminate the threading dislocation propagating upward from the first epitaxital layer.

### Claim 16

A ZnSe epitaxital semiconductor structure, comprising a Si substrate, a first SiGe epitaxital layer with Ge mole fraction of at least 70%, a second SiGe epitaxital layer with higher Ge mole fraction, and optionally a third SiGe epitaxital layer with Ge mole fraction higher than that of the second SiGe epitaxital layer, a pure Ge layer, and a ZnSe layer as the top layer, characterized in: the Ge mole fractions in the SiGe epitaxital layers are increased stepwise, and the total thickness of epitaxital layers, excluding ZnSe layer, is controlled to be below 3.0 μm.

### Claim 17 (depends on 1)

A ZnSe epitaxital semiconductor structure, comprising a Si substrate, a first SiGe epitaxital layer with Ge mole fraction of at least 70%, a second SiGe epitaxital layer with higher Ge mole fraction, and optionally a third SiGe epitaxital layer with Ge mole fraction higher than that of the second SiGe epitaxital layer, a pure Ge layer, and a ZnSe layer as the top layer, characterized in: the threading dislocation density is controlled to be below 106/cm2 by process as described in claim 1.

### Claim 18 (depends on 15)

A structure as described in claim 15, wherein ZnSe layer can be replaced by III–V groups heterogeneous epitaxital materials selected from the group consisting of ZnMgSe, ZnTe, ZnSSe, InSe, CdSe, ZnS, GaSe.

### Claim 19 (depends on 15)

A structure as described in claim 15, which is applicable to the manufacture of elements as white/blue/green light-emitting diodes (LED), visible-sensitivity emitter bipolar transistors and solar cells.

### Claim 20 (depends on 15)

A structure as described in claim 15, which is usable as chips of III–IV groups materials and in the integration of chips of III–V groups and IV group materials.

### Claim 21 (depends on 16)

A structure as described in claim 16, wherein ZnSe layer can be replaced by III–V groups heterogeneous epitaxital materials selected from the group consisting of ZnMgSe, ZnTe, ZnSSe, InSe, CdSe, ZnS, GaSe.

### Claim 22 (depends on 17)

A structure as described in claim 17, wherein ZnSe layer can be replaced by III–V groups heterogeneous epitaxital materials selected from the group consisting of ZnMgSe, ZnTe, ZnSSe, InSe, CdSe, ZnS, GaSe.

### Claim 23 (depends on 16)

A structure as described in claim 16, which is applicable to the manufacture of elements as white/blue/green light-emitting diodes (LED), visible-sensitivity emitter bipolar transistors and solar cells.

### Claim 24 (depends on 17)

A structure as described in claim 17, which is applicable to the manufacture of elements as white/blue/green light-emitting diodes (LED), visible-sensitivity emitter bipolar transistors and solar cells.

### Claim 25 (depends on 16)

A structure as described in claim 16, which is usable as chips of III–IV groups materials and in the integration of chips of III–V groups and IV group materials.

### Claim 26 (depends on 17)

A structure as described in claim 17, which is usable as chips of III–IV groups materials and in the integration of chips of III–V groups and IV group materials.