# US 7,071,086 B2 · Method of forming a metal gate structure with tuning of work function by silicon incorporation

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 7,071,086 B2
- Document ID: US7071086B2
- Status: Granted
- Kind: B2
- Application number: 10/420,721
- Filed: 2003-04-23
- Published: 2004-10-28
- Granted: 2006-07-04
- Earliest claimed: 2003-04-23
- Assignees: Advanced Micro Devices, Inc.
- Inventors: Christy Woo; Paul Besser; Minh van Ngo; James Pan; Jinsong Yin
- Web page: https://patentgrep.com/patent/US7071086B2

## CPC

- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 64/01316: {the conductor comprising a layer of elemental metal contacting the insulator, e.g. Ta, W, Mo or Al}
- H10D 64/01318: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314)}
- H10D 64/665: {the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum (having lateral variation H10D64/671)}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10P 32/30: Diffusion for doping of conductive or resistive layers
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method for forming a semiconductor structure having a metal gate with a controlled work function includes the step of forming a precursor having a substrate with active regions separated by a channel, a temporary gate over the channel and within a dielectric layer. The temporary gate is removed to form a recess with a bottom and sidewalls in the dielectric layer. A non-silicon containing metal layer is deposited in the recess. Silicon is incorporated into the metal layer and a metal is deposited on the metal layer. The incorporation of the silicon is achieved by silane treatments that are performed before, after or both before and after the depositing of the metal layer. The amount of silicon incorporated into the metal layer controls the work function of the metal gate that is formed.

## Claims

### Claim 1

A method of forming a semiconductor structure comprising the steps of forming a precursor having a substrate with active regions separated by a channel, and a temporary gate over the channel and within a dielectric layer:
removing the temporary gate to form a recess with a bottom and sidewalk in the dielectric layer;
pre-soaking the recess with silane (SiH4);
depositing a non-silicon metal containing metal layer in the recess after the recess has been pre-soak with silane;
depositing a metal on the metal layer; and
incorporating silicon into the metal layer; the incorporating including at least incorporating silicon provided by the pre-soaking of the recess.

### Claim 2 (depends on 1)

The method of claim 1, wherein the step of incorporating silicon further includes a pre-soak with SiH4 after the depositing of the non-silicon containing metal layer.

### Claim 3 (depends on 2)

The method of claim 2, wherein the step of incorporating silane further includes a plasma treatment alter the depositing of the non-silicon containing metal layer.

### Claim 4 (depends on 1)

The method of claim 1, wherein the step of incorporating silicon includes a plasma treatment after the deposition of the non-silicon containing metal layer.

### Claim 5 (depends on 1)

The method of claim 1, further comprising controlling an amount of silicon incorporation by controlling a number of silane treatments.

### Claim 6 (depends on 5)

The method of claim 5, wherein multiple silane treatments are performed on the metal layer.

### Claim 7 (depends on 1)

The method of claim 1, further comprising controlling silane treatment time to control an amount of silicon incorporation.

### Claim 8 (depends on 1)

The method of claim 1, further comprising controlling silane treatment temperature to control an amount of silicon incorporation.

### Claim 9 (depends on 8)

The method of claim 8, wherein the silane treatment temperature is controlled to be between about 250° C. to about 550° C.

### Claim 10 (depends on 1)

The method of claim 1, further comprising controlling the thickness of the non-silicon containing metal layer to control an amount of silicon incorporation.

### Claim 11 (depends on 1)

The method of claim 1, wherein the non-silicon containing metal layer includes one of Ta, W, Mo, Ru, Ti, TiN, TaN and Co.

### Claim 12 (depends on 2)

The method of claim 2, wherein the non-silicon containing metal layer includes one of Ta, W, Mo, Ru, Ti, TiN, TaN and Co.

### Claim 13 (depends on 12)

The method of claim 12, wherein the metal deposited on the metal layer is CU or a CU alloy.

### Claim 14 (depends on 1)

The method of claim 1, further comprising controlling silane treatment time to control an amount of silicon incorporation.