Predefined critical spaces in IC patterning to reduce line end pull back

A method of forming a semiconductor device, the method comprising the steps of:

• forming a layer to be patterned;
• forming a photosensitive layer over the layer to be patterned;
• patterning the photosensitive layer to form a pattern including a horizontal line and a vertical line without a space therebetween;
• transferring the pattern to the layer to be patterned;
• forming a second photosensitive layer over the pattern;
• patterning the second photosensitive layer to form a second pattern including a space aligned between the horizontal line and the vertical line;
• and
• transferring the second pattern to the layer to be patterned to form a third pattern including a horizontal line and a vertical line with a space therebetween, the space including a width dimension achievable at a resolution limit of lithography,
• wherein the horizontal line and the vertical line include critical dimensions that are less than critical dimensions achievable by lithography processes alone.