# US 7,071,072 B2 · Forming shallow trench isolation without the use of CMP > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,071,072 B2 - Document ID: US7071072B2 - Status: Granted - Kind: B2 - Application number: 10/710,001 - Filed: 2004-06-11 - Published: 2005-12-15 - Granted: 2006-07-04 - Earliest claimed: 2004-06-11 - Assignees: International Business Machines Corporation - Inventors: Renee T. Mo; Shreesh Narasimha - Web page: https://patentgrep.com/patent/US7071072B2 ## CPC - H10P 90/1906: {Preparing SOI wafers} - H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations} - H10W 10/061: {using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations} - H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations - H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers} - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Shallow trench isolation structures are formed without CMP by depositing a thick pad nitride and depositing oxide trench fill material such that: a) the material in the trenches is above the silicon surface by a process margin that allows for removal of trench fill in subsequent front end steps so that the final trench fill level is substantially coplanar with the silicon; and b) the oxide on the interior walls is easily removed, so that the pad nitride is removed in a wet etch. ## Claims ### Claim 1 A method of forming a set of insulator plugs in an isolation trench in a semiconductor substrate having a device layer, without the use of CMP, comprising the steps of: depositing a pad insulator layer having a pad thickness over said device layer surface; etching a set of isolation apertures through said pad insulator and said device layer to an isolation depth; depositing in a single deposition step an isolation insulator layer in said isolation apertures to a depth sufficient to fill said isolation apertures above said device layer by a first margin that is less than the thickness of said pad insulator and having a sidewall thickness on isolation aperture walls; etching said isolation insulator layer such that said sidewall thickness of said isolation insulator on said aperture walls is removed; whereby at least some of said isolation insulator remains disposed on a top surface of said pad insulator as a remaining portion of said isolation insulator layer; and remaining isolation plugs of said isolation insulator layer fill said isolation apertures with an isolation plug surface above said device layer surface by a second margin; and etching said pad insulator layer with an etchant that does not attack said isolation insulator layer, whereby said pad insulator and said remaining portion of said isolation insulator layer are removed in the same step and said isolation plugs fill said apertures without CMP. ### Claim 2 (depends on 1) A method according to claim 1, in which said semiconductor substrate is an SOI wafer in which said device layer is formed above a buried insulator layer. ### Claim 3 (depends on 2) A method according to claim 2, in which said pad thickness is such that said sidewall thickness is less than a sidewall threshold amount. ### Claim 4 (depends on 2) A method according to claim 2, in which said first margin is greater than said sidewall threshold amount. ### Claim 5 (depends on 1) A method according to claim 1, in which said semiconductor substrate is a bulk silicon wafer in which said device layer is formed in said silicon wafer. ### Claim 6 (depends on 5) A method according to claim 5, in which said pad thickness is such that said sidewall thickness is less than a sidewall threshold amount. ### Claim 7 (depends on 5) A method according to claim 5, in which said first margin is greater than said sidewall threshold amount. ### Claim 8 (depends on 1) A method according to claim 1, in which said pad thickness is such that said sidewall thickness is less than a sidewall threshold amount. ### Claim 9 (depends on 1) A method according to claim 1, in which said first margin is greater than said sidewall threshold amount. ### Claim 10 A method of forming a set of insulator plugs in an isolation trench in a semiconductor substrate having a device layer, without the use of CMP, comprising the steps of: depositing a pad insulator layer having a pad thickness; implanting said pad insulator with ions such that implanted areas of said pad insulator have an etch rate substantially greater than unimplanted areas of said pad insulator; etching a set of isolation apertures through said device layer to an isolation depth; depositing in a single deposition step an insulator layer in said isolation apertures to a depth sufficient to fill said isolation apertures above said device layer by a first margin that is less than the thickness of said pad insulator and having a sidewall thickness on isolation aperture walls; etching said insulator layer such that said sidewall thickness of said insulator on said isolation aperture walls is removed; whereby at least some of said isolation insulator remains disposed on a top surface of said pad insulator as a remaining portion of said isolation insulator layer; and remaining insulator plugs of said insulator layer fill said isolation apertures above said device layer; and etching said pad insulator layer with an etchant that does not attack said insulator layer, whereby said pad insulator and said remaining portion of said isolation insulator layer are removed and said isolation plugs fill said isolation apertures without CMP. ### Claim 11 (depends on 10) A method according to claim 10, in which at least areas of pad nitride disposed between apertures separated by greater than a minimum active area distance are implanted. ### Claim 12 (depends on 10) A method according to claim 10, in which only areas of pad nitride disposed between apertures separated by greater than a minimum active area distance are implanted. ### Claim 13 (depends on 12) A method according to claim 12, in which said pad thickness is such that said sidewall thickness is less than a sidewall threshold amount. ### Claim 14 (depends on 12) A method according to claim 12, in which said first margin is greater than said sidewall threshold amount. ### Claim 15 (depends on 10) A method according to claim 10, in which said ions have an implantation energy such that less than a threshold amount of ions penetrate said device layer. ### Claim 16 (depends on 10) A method according to claim 10, in which said ions have an implantation energy such that at least a threshold concentration of ions extend throughout said pad insulator layer. ### Claim 17 (depends on 10) A method according to claim 10, in which said pad thickness is such that said sidewall thickness is less than a sidewall threshold amount. ### Claim 18 (depends on 10) A method according to claim 10, in which said first margin is greater than said sidewall threshold amount. ### Claim 19 (depends on 10) A method according to claim 10, in which said implanted areas are formed only in areas of pad nitride disposed between isolation apertures separated by greater than a minimum active area distance. ### Claim 20 A method of forming a set of isolation plugs in an isolation trench in a semiconductor substrate having a device layer without the use of CMP comprising the steps of: depositing a pad insulator layer having a pad thickness; etching a set of isolation apertures through said device layer to an isolation depth; depositing an isolation insulator layer in said isolation apertures to a depth sufficient to fill said isolation apertures above said device layer by a first margin and having a sidewall thickness on isolation aperture walls; etching said isolation insulator layer such that said sidewall thickness of said isolation insulator on said isolation aperture walls is removed and remaining isolation plugs of said isolation insulator layer fill said apertures substantially coplanar with said device layer, without CMP; forming a set of field apertures in areas of pad insulator disposed between isolation apertures separated by a minimum active area distance; and etching said pad insulator layer with an etchant that does not attack said isolation insulator layer, whereby said pad insulator is removed and said isolation plugs fill said aperture without CMP. ### Claim 21 (depends on 20) A method according to claim 20, in which said step of etching said isolation insulator layer such that said sidewall thickness of said isolation insulator on said isolation aperture walls is removed and remaining isolation plugs of said insulator layer fill said apertures substantially coplanar with said device layer is performed after said step of forming a set of field apertures in areas of pad insulator disposed between isolation apertures separated by a minimum active area distance. ### Claim 22 A method of forming a set of insulator plugs in an isolation trench in a semiconductor substrate having a device layer comprising the steps of: depositing a pad insulator layer having a pad thickness; implanting said pad insulator with ions such tat implanted areas of said pad insulator have an etch rate substantially greater than unimplanted areas of said pad insulator; etching a set of isolation apertures through said device layer to an isolation depth; depositing an insulator layer in said isolation apertures to a depth sufficient to fill said isolation apertures above said device layer by a first margin and having a sidewall thickness on isolation aperture walls; etching said insulator layer such that said sidewall thickness of said insulator on said isolation aperture walls is removed and remaining insulator plugs of said insulator layer fill said isolation apertures above said device layer; and etching said pad insulator layer with an etchant that does not attack said insulator layer, whereby said pad insulator is removed and said isolation plugs fill said aperture without CMP, in which said implanted areas are formed only in areas of pad nitride disposed between isolation apertures separated by greater than a minimum active area distance in which said step of etching said insulator layer such that said sidewall thickness of said insulator on said aperture walls is removed and remaining isolation plugs of said insulator layer fill said apertures substantially coplanar with said device layer is performed before said step of forming a set of apertures in areas of pad insulator disposed between isolation apertures separated by a minimum active area distance.