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US 7,071,070 B2Granted
Method of fabricating capacitor
AssigneeUnited Microelectronics Corp.
InventorJing-Horng Gau
Life of this patent
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Abstract
A method of fabricating a capacitor is described. A dielectric layer is formed over a substrate. An upper electrode having multiple openings therein is formed over the dielectric layer. Then, a doping step is performed to the substrate through the openings to form a single doped region as a lower electrode in the substrate under the upper electrode.
Claims26
A method of fabricating a capacitor, comprising:
- forming a dielectric layer on a semiconductor substrate;
- forming an upper electrode on the dielectric layer, the upper electrode having a plurality of opening therein;
- performing a doping step to the semiconductor substrate through the openings to form a single doped region as a lower electrode in the semiconductor substrate under the upper electrode;
- and
- forming a plurality of metal silicide layers on portions of the single doped region within the openings.
2 more elements
A method of fabricating a capacitor, comprising:
- forming a dielectric layer on a silicon substrate;
- forming an upper electrode on the dielectric layer, the upper electrode comprising doped polysilicon and having a plurality of opening therein;
- performing a doping step to the substrate through the openings to form a single doped region as a lower electrode in the substrate under the upper electrode;
- forming a spacer on a sidewall of each opening in the upper electrode;
- and
- performing a self-aligned silicide (salicide) process to form a plurality of metal silicide layers on the upper electrode and portions of the single doped region within the openings.
3 more elements
A method of fabricating a capacitor, comprising:
- forming a dielectric layer on a silicon substrate;
- forming an upper electrode on the dielectric layer, the upper electrode comprising doped polysilicon and having a plurality of opening therein;
- performing a doping step to the substrate through the openings to form a single doped region as a lower electrode in the substrate under the upper electrode;
- forming a liner layer on a sidewall of each opening in the upper electrode;
- forming a spacer on each liner layer on a sidewall of an opening;
- removing the spacer;
- and
- performing a self-aligned silicide (salicide) process to form a plurality of metal silicide layers on the upper electrode and portions of the single doped region within the openings.
5 more elements
Dependencies are inferred from the claim text.