# US 7,071,066 B2 · Method and structure for forming high-k gates

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- Number: US 7,071,066 B2
- Document ID: US7071066B2
- Status: Granted
- Kind: B2
- Application number: 10/662,845
- Filed: 2003-09-15
- Published: 2005-03-17
- Granted: 2006-07-04
- Earliest claimed: 2003-09-15
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Ming-Fang Wang; Chia-Lin Chen; Chih-Wei Yang; Chi-Chun Chen; Tuo-Hung Hou; Yeou-Ming Lin; Liang-Gi Yao; Shih-Chang Chen
- Web page: https://patentgrep.com/patent/US7071066B2

## CPC

- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D 64/0134: {with a treatment, e.g. annealing, after the formation of the insulator and before the formation of the conductor}
- H10D 64/01342: {by deposition, e.g. evaporation, ALD or laser deposition (H10D64/01344 takes precedence)}
- H10D 64/685: {being perpendicular to the channel plane}
- H10P 14/6339: {deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD}
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method for forming an improved gate stack structure having improved electrical properties in a gate structure forming process A method for forming a high dielectric constant gate structure including providing a silicon substrate comprising exposed surface portions; forming an interfacial layer over the exposed surface portions having a thickness of less than about 10 Angstroms; forming a high dielectric constant metal oxide layer over the interfacial layer having a dielectric constant of greater than about 10; forming a barrier layer over the high dielectric constant metal oxide layer; forming an electrode layer over the barrier layer; and, etching according to an etching pattern through a thickness of the electrode layer, barrier layer, high dielectric constant material layer, and the interfacial layer to form a high dielectric constant gate structure.

## Claims

### Claim 1

A method for forming a gate stack having improved electrical properties in a gate structure forming process comprising the steps of:
providing a semiconductor substrate;
forming a metal oxide layer over an exposed portion of the semiconductor substrate; and
forming a silicon-containing electrode layer over the metal oxide layer by depositing a silicon layer and introducing a nitrogen containing ambient simultaneously.

### Claim 2 (depends on 1)

The method of claim 1, wherein the metal oxide layer comprises a dielectric constant of greater than about 20.

### Claim 3 (depends on 1)

The method of claim 1, wherein the metal oxide is formed having a thickness of about 20 Angstroms to about 100 Angstroms.

### Claim 4 (depends on 1)

The method of claim 1, wherein the gate stack including the metal oxide layer is formed to have a dielectric thickness equivalent to a silicon dioxide dielectric thickness of less than about 20 Angstroms.

### Claim 5 (depends on 3)

The method of claim 3, wherein the metal oxide is selected from the group consisting of tantalum oxides, titanium oxides, zirconium oxides, hafnium oxides, and yttrium oxides.

### Claim 6 (depends on 5)

The method of claim 5, wherein the metal oxide is formed from one of a metal-organic CVD method and an atomic layer deposition (ALD) method.

### Claim 7 (depends on 6)

The method of claim 6, wherein an ozone containing oxidation process is carried out to treat the metal oxide layer following the formation of the metal oxide layer.

### Claim 8 (depends on 1)

The method of claim 1, wherein a layer comprising aluminum oxide is formed over the metal oxide layer.

### Claim 9 (depends on 8)

The method of claim 8, wherein the aluminum oxide layer is formed having a thickness of about 5 Angstroms to about 15 Angstroms.

### Claim 10

A method for forming a gate stack having improved electrical properties in a gate structure forming process comprising the steps of:
providing a semiconductor substrate;
forming a metal oxide layer over an exposed portion of the semiconductor substrate; and
depositing a polysilicon electrode over the metal oxide layer by a low pressure chemical vapor deposition (LPCVD) process simultaneously in association with a nitrogen containing ambient.

### Claim 11 (depends on 10)

The method of claim 10, wherein the LPCVD process comprises a cold-wall and a hot-wall configuration.