Dual-bit non-volatile memory cell and method of making the same

A method for fabricating a dual-bit non-volatile memory cell, the method comprising:

• forming a dummy gate, having an upper surface and two sidewalls, on a substrate;
• forming a stack of layers, having at least an oxide silicon layer and a silicon nitride layer overlying the oxide silicon layer, on the upper surface and two sidewalls of the dummy gate and exposed portions of the substrate;
• forming a dummy oxide overlying the stack of layers;
• etching a portion of the dummy oxide, a portion of the stack of layers on the two sidewalls of the dummy gate, and a portion of the dummy gate using a first etching process, wherein the bottom of the silicon nitride layer is utilized as a stop layer;
• removing the dummy gate such that the stack of layers has a first opening to expose a portion of the substrate;
• forming a gate oxide layer on the first opening such that the gate oxide layer has a recess within the first opening;
• forming a first polysilicon layer on the gate oxide layer;
• forming a control gate on the recess using the first polysilicon layer;
• forming a second oxide silicon layer on the surface of the control gate and the stack of the layers;
• forming a second polysilicon layer on the second oxide silicon layer;
• and
• performing a self-aligned etching to anisotropically etch the second polysilicon layer to form dual split-gates on the second oxide silicon layer, separated from the control gate by the second oxide silicon layer.