# US 7,071,054 B2 · Methods of fabricating MIM capacitors in semiconductor devices

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 7,071,054 B2
- Document ID: US7071054B2
- Status: Granted
- Kind: B2
- Application number: 11/027,524
- Filed: 2004-12-30
- Published: 2005-06-30
- Granted: 2006-07-04
- Earliest claimed: 2003-12-31
- Assignees: Dongbu Electronics Co., Ltd.
- Inventors: Jeong Ho Park
- Web page: https://patentgrep.com/patent/US7071054B2

## CPC

- H10W 20/086: {involving buried masks}
- H10D 1/042: {using deposition processes to form electrode extensions}
- H10D 1/716: {having vertical extensions}
- H10W 20/496: {Capacitor integral with wiring layers}
- H10B 12/03: {Making the capacitor or connections thereto}
- H10B 12/50: {Peripheral circuit region structures}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

Methods of fabricating an MIM capacitor and a dual damascene structure of a semiconductor device are disclosed. According to one example, a method includes depositing a first insulating layer on a semiconductor substrate; forming a lower interconnect through the first insulating layer; sequentially depositing a second insulating layer, a third insulating layer, and a fourth insulating layer; forming a first mask pattern over the fourth insulating layer; forming a first dual damascene pattern by etching the fourth insulating layer; depositing a fifth insulating layer; forming a second mask pattern over the fifth insulating layer; forming dual damascene structure by performing an etching process; sequentially depositing a second conducting layer and a dielectric layer on the dual damascene structure; selectively removing some portion of the dielectric layer; depositing a third conducting layer over the dielectric layer; and planarizaing the top surface of the third conducting layer, the dielectric layer, and the second conducting layer by performing a CMP process.

## Claims

### Claim 1

A method of fabricating a metal-insulator-metal capacitor of a semiconductor device comprising:
depositing a first insulating layer on a semiconductor substrate having at least one predetermined structure;
forming a first conducting layer as a lower interconnect through the first insulating layer;
sequentially depositing a second insulating layer, a third insulating layer, and a fourth insulating layer over the first insulating layer and the first conducting layer;
forming a first mask pattern over the fourth insulating layer;
forming a first dual damascene pattern by etching the fourth insulating layer using the first mask pattern as a mask;
depositing a fifth insulating layer over the first dual damascene pattern;
forming a second mask pattern over the fifth insulating layer;
forming a dual damascene structure by performing an etching process using the second mask pattern and the first dual damascene pattern as a mask, respectively;
sequentially depositing a second conducting layer and a dielectric layer along a surface of the dual damascene structure;
selectively removing some portion of the dielectric layer so that the dielectric layer remains on an area for the capacitor;
depositing a third conducting layer over the dielectric layer; and
planarizing a top surface of the third conducting layer, the dielectric layer, and the second conducting layer by performing a chemical mechanical polish process.

### Claim 2 (depends on 1)

A method as defined by claim 1, further comprising depositing an antireflection coating before the first mask pattern is formed on the fourth insulating layer.

### Claim 3 (depends on 1)

A method as defined by claim 1, further comprising depositing an antireflection coating before the second mask pattern is formed on the fifth insulating layer.

### Claim 4 (depends on 1)

A method as defined by claim 1, wherein the second and the fourth insulating layers are used as a etch-stop layers, respectively and made of nitride, silicon carbide (SiC), or aluminum oxide.

### Claim 5 (depends on 1)

A method as defined by claim 1, wherein the third insulating layer is used as an interlayer dielectric layer and made of silicon oxide.

### Claim 6 (depends on 1)

A method as defined by claim 1, wherein the fifth insulating layer is used as an interlayer dielectric layer and made of silicon oxide.

### Claim 7 (depends on 1)

A method as defined by claim 1, wherein the chemical mechanical polish process is performed until the fifth insulating layer is exposed.

### Claim 8 (depends on 1)

A method as defined by claim 1, wherein the dual damascene structure comprises a plurality of via holes.

### Claim 9 (depends on 8)

A method as defined by claim 8, wherein the plurality of via holes comprise at least one stepwise-shaped via hole, an upper part of which is wider than a lower part thereof.

### Claim 10 (depends on 1)

A method as defined by claim 1, wherein selectively removing some portion of the dielectric layer is performed by using a wet etching process and a photoresist pattern which covers the area for the capacitor and exposes another area.

### Claim 11 (depends on 1)

A method as defined by claim 1, wherein the second conducting layer is a single layer made of TaN, TiN or WN, or a multi-layer comprising TaN, TiN, or WN, and used as a lower electrode of the capacitor.

### Claim 12 (depends on 1)

A method as defined by claim 1, wherein the dielectric layer is made of nitride, tetra ethoxy silane, tantalum oxide, or aluminum oxide.

### Claim 13 (depends on 1)

A method as defined by claim 1, wherein the third conducting layer is a single layer of copper or a multi-layer comprising copper, and used as an upper electrode of the capacitor.