# US 7,071,052 B2 · Resistor with reduced leakage

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- Number: US 7,071,052 B2
- Document ID: US7071052B2
- Status: Granted
- Kind: B2
- Application number: 10/667,871
- Filed: 2003-09-22
- Published: 2005-02-24
- Granted: 2006-07-04
- Earliest claimed: 2003-08-18
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Yee-Chia Yeo; Chenming Hu
- Web page: https://patentgrep.com/patent/US7071052B2

## CPC

- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10D 1/47: Resistors having no potential barriers
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A resistor 100 is formed in a semiconductor layer 106, e.g., a silicon layer on an SOI substrate. A body region 108 is formed in a portion of the semiconductor layer 106 and is doped to a first conductivity type (e.g., n-type or p-type). A first contact region 110, which is also doped to the first conductivity type, is formed in the semiconductor layer 106 adjacent the body region 108. A second contact region 112 is also formed in the semiconductor layer 106 and is spaced from the first contact region 110 by the body region 108. A dielectric layer 116 overlies the body region and is formed from a material with a relative permittivity greater than about 8. An electrode 114 overlies the dielectric 116.

## Claims

### Claim 1

A method of forming a resistor, the method comprising:
providing a silicon-on-insulator substrate that includes a silicon layer overlying an insulator layer;
forming a resistor body of a first conductivity type in a portion of the silicon layer;
forming a dielectric layer overlying the body region, the dielectric layer comprising a material with a relative permittivity greater than about 8;
forming a top electrode on the dielectric layer, the top electrode comprising a conductive material; and
forming a pair of doped regions of the first conductivity type oppositely adjacent the body region.

### Claim 2 (depends on 1)

The method of claim 1 wherein forming the resistor body comprises:
forming an active region;
forming isolation regions surrounding the active region; and
doping the active region.

### Claim 3 (depends on 2)

The method of claim 2 wherein doping the active region employs an ion implantation with a dose in the range of about 1013 to about 1016 cm−2.

### Claim 4 (depends on 1)

The method of claim 1 wherein forming the dielectric layer comprises a chemical vapor deposition step.

### Claim 5 (depends on 1)

The method of claim 1 wherein forming the dielectric layer comprises a sputtering deposition step.

### Claim 6 (depends on 1)

The method of claim 1 wherein forming the dielectric layer comprises:
forming an interfacial oxide layer; and
forming a high permittivity dielectric layer.

### Claim 7 (depends on 1)

The method of claim 1 wherein forming the pair of doped regions comprises:
doping a portion of the silicon layer not covered by the top electrode;
forming spacers on sidewalls of the top electrode; and
doping a portion of the silicon layer not covered by the top electrode and the spacers.

### Claim 8 (depends on 7)

The method of claim 7 wherein the spacers comprise silicon nitride.

### Claim 9 (depends on 7)

The method of claim 7 further comprising:
depositing an etch-stop layer over the top electrode and the spacers;
forming an inter-layer dielectric over the etch-stop layer;
forming contact holes in the inter-layer dielectric layer; and
filling the contact holes with a conductive material to form contact plugs.

### Claim 10 (depends on 9)

The method of claim 9 wherein the etch-stop layer comprises silicon nitride.

### Claim 11 (depends on 9)

The method of claim 9 wherein the inter-layer dielectric comprises silicon oxide.

### Claim 12 (depends on 9)

The method of claim 9 wherein a first contact plug electrically contacts one of the pair of doped regions and a second contact plug electrically contacts the top electrode, said first and second contact plugs being electrically connected.

### Claim 13 (depends on 1)

The method of claim 1 wherein the insulator layer comprises silicon oxide.

### Claim 14 (depends on 1)

The method of claim 1 wherein the insulator layer has a thickness of less than about 1200 angstroms.

### Claim 15 (depends on 1)

The method of claim 1 wherein the silicon layer has a thickness in the range of about 20 angstroms to about 1000 angstroms.

### Claim 16 (depends on 1)

The method of claim 1 wherein the top electrode comprises a doped semiconductor.

### Claim 17 (depends on 1)

The method of claim 1 wherein the top electrode comprises a metal selected from the group consisting of molybdenum, tungsten, titanium, tantalum, platinum, and hafnium.

### Claim 18 (depends on 1)

The method of claim 1 wherein the top electrode comprises a metallic nitride selected from the group consisting of molybdenum nitride, tungsten nitride, titanium nitride, tantalum nitride, or combinations thereof.

### Claim 19 (depends on 1)

The method of claim 1 wherein the top electrode comprises a metallic silicide selected from the group consisting of nickel silicide, cobalt silicide, tungsten silicide, titanium silicide, tantalum silicide, platinum silicide, and erbium silicide, and combinations thereof.

### Claim 20 (depends on 1)

The method of claim 1 wherein the top electrode comprises a metallic oxide selected from the group comprising of ruthenium oxide, and indium tin oxide, and combinations thereof.

### Claim 21 (depends on 1)

The method of claim 1 wherein the dielectric layer comprises a material selected from the group consisting of aluminum oxide, hafnium oxide, hafnium oxynitride, hafnium silicate, zirconium oxide, zirconium oxynitride, and zirconium silicate, and combinations thereof.

### Claim 22 (depends on 1)

The method of claim 1 wherein the dielectric layer has a relative permittivity of larger than about 10.

### Claim 23 (depends on 1)

The method of claim 1 wherein the dielectric layer has a relative permittivity of larger than about 20.

### Claim 24 (depends on 1)

The method of claim 1 wherein the dielectric has a physical thickness greater than about 5 angstroms.

### Claim 25 (depends on 24)

The method of claim 24 wherein the dielectric has a physical thickness greater than about 20 angstroms.

### Claim 26 (depends on 25)

The method of claim 25 wherein the dielectric has a physical thickness greater than about 40 angstroms.

### Claim 27 (depends on 1)

The method of claim 1 wherein the electrode has a width greater than about 0.1 microns.

### Claim 28 (depends on 1)

The method of claim 1 wherein the electrode has a width greater than about 1 micron.

### Claim 29 (depends on 1)

The method of claim 1 the electrode has a length greater than about 0.1 microns.

### Claim 30 (depends on 2)

The method of claim 2 wherein the electrode has a length greater than about 1 micron.
