# US 7,071,048 B2 · Methods of fabricating fin field effect transistors having capping insulation layers

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- Number: US 7,071,048 B2
- Document ID: US7071048B2
- Status: Granted
- Kind: B2
- Application number: 10/936,033
- Filed: 2004-09-08
- Published: 2005-05-05
- Granted: 2006-07-04
- Earliest claimed: 2003-10-31
- Assignees: Samsung Electronics Co., Ltd.
- Inventors: Yong-Hoon Son; Si-Young Choi; Byeong-Chan Lee; Deok-Hyung Lee; In-Soo Jung
- Web page: https://patentgrep.com/patent/US7071048B2

## CPC

- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 86/00: Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A field effect transistor includes a vertical fin-shaped semiconductor active region having an upper surface and a pair of opposing sidewalls on a substrate, and an insulated gate electrode on the upper surface and opposing sidewalls of the fin-shaped active region. The insulated gate electrode includes a capping gate insulation layer having a thickness sufficient to preclude formation of an inversion-layer channel along the upper surface of the fin-shaped active region when the transistor is disposed in a forward on-state mode of operation. Related fabrication methods are also discussed.

## Claims

### Claim 1

A method of forming a semiconductor device, the method comprising:
forming a fin active region by selectively etching a region of a substrate;
forming a conformal liner layer on the substrate;
forming an insulation layer on the liner layer to fill the etched region of the substrate;
planarizing the insulation layer and the liner layer until a top surface of the fin active region is exposed to form a preliminary liner and device isolation layer sequentially stacked on a sidewall of the fin active region;
forming a capping insulation layer on the top surface of the fin active region;
selectively recessing the preliminary liner to form a liner on a portion of the sidewall of the fin active region for exposing an upper portion of the sidewall of the fin active region;
forming a gate insulation layer on at least the exposed surface of the fin active region; and
forming a gate electrode crossing over the fin active region,
wherein the capping insulation layer is formed to a thickness thicker than a thickness of the gate insulation layer.

### Claim 2 (depends on 1)

A method according to claim 1, further comprising the following before forming the conformal liner layer:
forming a buffer oxide on the whole substrate having the fin active region,
wherein planarizing the insulation layer and conformal liner layer comprises planarizing the insulation layer, conformal liner layer and buffer oxide until the top surface of the fin active region is exposed, and wherein recessing the preliminary liner comprises recessing the preliminary liner and buffer oxide to expose the upper portion of the sidewall of the fin active region.

### Claim 3 (depends on 1)

A method according to claim 1, further comprising forming a supplemental insulation layer on the substrate to fill a portion of the etched region of the substrate before forming the conformal liner layer.

### Claim 4 (depends on 1)

A method according to claim 1, wherein forming the insulation layer and liner layer comprises:
planarizing the insulation layer by chemical mechanical polishing process until the conformal liner layer is exposed;
forming the device isolation layer by recessing the planarized insulation layer; and
performing an etch back process at the exposed conformal liner layer until the top surface of the fin active region is exposed to form the preliminary liner.

### Claim 5 (depends on 1)

A method according to claim 1, wherein the capping insulation layer is formed by performing a thermal oxidation process at the exposed top surface of the fin active region.

### Claim 6 (depends on 1)

A method according to claim 1, after forming the gate electrode, further comprising:
implanting impurity ions using the gate electrode as a mask to form source/drain regions at the fin active region on both sides of the gate electrode.

### Claim 7

A method of forming a semiconductor device, the method comprising:
selectively etching a substrate having first and second regions to form a fin active region in the first region and a planar active region in the second region;
forming a conformal liner layer on the substrate;
forming a insulation layer on the conformal liner layer to fill the etched region of the substrate;
planarizing the insulation layer and conformal liner layer until top surfaces of the fin and planar active regions are exposed to form a preliminary first liner and a first device isolation layer sequentially stacked on a sidewall of the fin active region and a second liner and second device isolation layer sequentially stacked on a sidewall of the planar active region;
forming a capping insulation layer on a top surface of the fin active region;
selectively recessing the preliminary first liner to form a first liner on a portion of the sidewall of the fin active region for exposing a upper portion of the sidewall of the fin active region;
forming a first gate insulation layer on at least the exposed surface of the fin active region and a second gate insulation layer on a top surface of the planar active region; and
forming a first gate electrode crossing over the capping insulation layer and fin active region and a second gate electrode crossing over the planar active region,
wherein the capping insulation layer is formed to a thickness thicker than a thickness of the first and second gate insulation layers.

### Claim 8 (depends on 7)

A method according to claim 7, before forming the conformal liner layer, further comprising:
forming a buffer oxide on the substrate having the fin and planar active regions,
wherein planarizing the insulation layer and conformal liner layer comprises planarizing the insulation layer, conformal liner layer and buffer oxide until the top surfaces of the fin and planar active regions, and wherein recessing the preliminary first liner comprises successively recessing the preliminary first liner and the buffer oxide until the upper portion of the sidewall of the fin active region.

### Claim 9 (depends on 7)

A method according to claim 7, further comprising:
forming a supplemental insulation layer on the substrate to fill a portion of the etched region of the substrate before forming the conformal liner layer.

### Claim 10 (depends on 7)

A method according to claim 7, wherein planarizing the insulation layer and the conformal liner layer comprises:
planarizing the insulation layer by chemical mechanical polishing process until the conformal liner layer is exposed;
recessing the planarized insulation layer to form the first and second device isolation layers; and
performing an etch back process on the exposed conformal liner layer until the top surfaces of the fin and planar active regions are exposed to form the first and second liners.

### Claim 11 (depends on 7)

A method according to claim 7, wherein forming the capping insulation layer comprises:
forming an oxidation barrier layer on the substrate;
patterning the oxidation barrier layer to expose the top surface of the fin active region;
performing thermal oxidation process on the exposed top surface of the fin active region to form the capping insulation layer; and
removing the patterned oxidation barrier layer.

### Claim 12 (depends on 11)

A method according to claim 11, wherein removing the patterned oxidation barrier layer and recessing the preliminary first liner are performed simultaneously.

### Claim 13 (depends on 7)

A method according to claim 7, further comprising the following after forming the first and second gate electrode:
implanting impurity ions using the first gate electrode as mask to form first source/drain regions in the fin active region on both sides of the first gate electrode; and
implanting impurity ions using the second gate electrode as mask to form second source/drain regions in the planar active region on both sides of the second gate electrode.

### Claim 14 (depends on 13)

A method according to claim 13, wherein the first and second source/drain regions are formed simultaneously.

### Claim 15

A method of forming a vertical channel field effect transistor on a fin-shaped active region of a semiconductor substrate, the method comprising:
forming an insulated gate electrode on an upper surface and opposing sidewalls of the fin-shaped active region, wherein forming the insulated gate electrode comprises forming a capping gate insulation layer on the upper surface of the fin-shaped active region to a thickness sufficient to preclude formation of an inversion-layer channel along the upper surface when the transistor is disposed in a forward on-state mode of operation; and
forming a sidewall gate insulation layer on sidewalls of the fin-shaped active region having a thickness similar to the thickness of the capping gate insulation layer,
wherein forming the capping gate insulation layer further comprises forming the capping gate insulation layer of a material having a higher dielectric strength than the sidewall gate insulation layer.

### Claim 16

A method of forming a vertical channel field effect transistor on a fin-shaped active region of a semiconductor substrate, the method comprising:
forming a buffer oxide layer on the fin-shaped active region of the substrate;
forming a liner layer on the buffer oxide layer;
forming an insulation layer on the liner layer;
planarizing the insulation layer, the liner layer, and the buffer oxide layer to expose an upper surface of the fin-shaped active region;
forming a capping gate insulation layer on the upper surface of the fin-shaped active region to a thickness sufficient to preclude formation of an inversion-layer channel along the upper surface when the transistor is disposed in a forward on-state mode of operation;
recessing the liner layer to expose a portion the buffer oxide layer on upper sidewalls of the fin-shaped active region;
removing the exposed portion of the buffer oxide layer to expose the upper sidewalls of the fin-shaped active region;
forming a sidewall gate insulation layer on the exposed upper sidewalls of the fin-shaped active region; and
forming a gate electrode on the upper surface and opposing sidewalls of the fin-shaped active region,
wherein forming the capping gate insulation layer further comprises forming the capping gate insulation layer to a thickness greater than a thickness of the sidewall gate insulation layer.

### Claim 17 (depends on 16)

The method of claim 16, wherein forming the capping gate insulation layer comprises thermally oxidizing the upper surface of the fin-shaped active region.

### Claim 18 (depends on 16)

The method of claim 16, further comprising:
forming a supplemental insulation layer on the buffer oxide layer prior to forming the conformal liner layer.

### Claim 19 (depends on 16)

Method of claim 16, wherein the substrate includes a planar active region adjacent the fin-shaped active region and the method further comprises the following after planarizing:
forming an oxidation barrier layer on the fin active region and the planar active region; and
patterning the oxidation barrier layer to expose the top surface of the fin active region,
wherein recessing the liner layer comprises simultaneously recessing the conformal liner layer on the fin-shaped active region and the oxidation barrier layer on the planar active region.

### Claim 20

A method of forming semiconductor devices on a semiconductor substrate, comprising:
selectively etching the substrate to form a fin-shaped active region and a planar active region;
forming a buffer oxide layer on the fin-shaped active region and the planar active region;
forming a liner layer on the buffer oxide layer;
forming a insulation layer on the liner layer;
planarizing the insulation layer, the liner layer, and the buffer oxide layer to expose upper surfaces of the fin-shaped active region and the planar active region;
forming an oxidation barrier layer on the fin active region and the planar active region;
patterning the oxidation barrier layer to expose the upper surface of the fin active region; and
forming an insulated gate electrode on the upper surface and opposing sidewalls of the fin-shaped active region, wherein forming the insulated gate electrode comprises:
forming a capping gate insulation layer on the upper surface of the fin-shaped active region to a thickness sufficient to preclude formation of an inversion-layer channel along the upper surface when the transistor is disposed in a forward on-state mode of operation;
recessing the liner layer on the fin-shaped active region to expose a portion of the buffer oxide layer on upper sidewalls of the fin-shaped active region;
removing the exposed portion of the buffer oxide layer to expose the upper sidewalls of the fin-shaped active region;
forming a sidewall gate insulation layer on the exposed upper sidewalls of the fin-shaped active region; and
forming a gate electrode on the upper surface and upper sidewalls of the fin-shaped active region;
wherein a thickness of the capping gate insulation layer is greater than a thickness of the sidewall gate insulation layer.