# US 7,071,046 B2 · Method of manufacturing a MOS transistor

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- Number: US 7,071,046 B2
- Document ID: US7071046B2
- Status: Granted
- Kind: B2
- Application number: 10/904,620
- Filed: 2004-11-18
- Published: 2006-05-18
- Granted: 2006-07-04
- Earliest claimed: 2004-11-18
- Assignees: United Microelectronics Corp.
- Inventors: Neng-Hui Yang; Huan-Shun Lin; Hsiang-Ying Wang
- Web page: https://patentgrep.com/patent/US7071046B2

## CPC

- H10D 30/608: {having non-planar bodies, e.g. having recessed gate electrodes}
- H10D 30/0227: {having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method of manufacturing a MOS transistor, comprising the steps of providing a semiconductor substrate, forming a gate structure on the semiconductor substrate, performing an implantation to form two implanted regions in the semiconductor substrate respectively adjacent to the gate structure, performing an etching process to remove each implanted region and form a trench, and performing a selective epitaxial growth to fill epitaxial crystal into the trenches, thereby forming a source/drain of the MOS transistor.

## Claims

### Claim 1

A method of manufacturing a MOS transistor, comprising:
providing a semiconductor substrate;
forming a gate structure on the semiconductor substrate;
forming an oxide-nitride-oxide (ONO) offset spacer on each sidewall of the gate structure;
performing an implantation process to form two implanted regions in the semiconductor substrate respectively adjacent to the oxide-nitride-oxide (ONO) offset spacers;
performing an etching process to remove each implanted region and form a trench; and
performing a selective epitaxial growth to fill epitaxial crystal into the trenches, thereby forming a source and a drain of the MOS transistor.

### Claim 2 (depends on 1)

The method of claim 1 wherein the gate structure comprises a gate oxide and a gate electrode on the gate oxide, and a cap layer is formed on the top surface of the gate electrode.

### Claim 3 (depends on 1)

The method of claim 1 wherein a dopant selected from the atom or an ion of boron, germanium, arsenic, phosphorus, antimony, or xenon is used in the implantation process.

### Claim 4 (depends on 1)

The method of claim 1 wherein the implantation process comprises a preamorphizing implantation to amorphize the implanted regions.

### Claim 5 (depends on 1)

The method of claim 1 wherein the implantation process is a tilt-angle implantation process and the trench is partly beneath the oxide-nitride-oxide offset spacer.

### Claim 6 (depends on 1)

The method of claim 1, after the implantation process, further comprising a step of annealing.

### Claim 7 (depends on 6)

The method of claim 6 wherein a profile of the source and the drain of the MOS transistor is controlled by an implanting species, implanting dosage, implanting energy, implanting tilt angle, annealing temperature, or annealing time.

### Claim 8 (depends on 6)

The method of claim 6 wherein the annealing comprises rapid thermal processing at a temperature between 1070° C. and 1100° C.

### Claim 9 (depends on 1)

The method of claim 1 wherein the etching process is a wet etching process.

### Claim 10 (depends on 9)

The method of claim 9 wherein a hot phosphoric acid solution is used as an etchant in the wet etching process.

### Claim 11 (depends on 1)

The method of claim 1 wherein the etching process is a dry etching process.

### Claim 12 (depends on 1)

The method of claim 1 wherein the epitaxial crystal comprises at least one of silicon and germanium.

### Claim 13 (depends on 1)

The method of claim 1 wherein the epitaxial crystal comprises at least one of silicon and carbon.

### Claim 14 (depends on 1)

The method of claim 1 wherein the epitaxial crystal further comprises a dopant.

### Claim 15 (depends on 12)

The method of claim 12 wherein the MOS transistor is a PMOS transistor.

### Claim 16 (depends on 13)

The method of claim 13 wherein the MOS transistor is a NMOS transistor.

### Claim 17

A method of forming source/drain regions in a semiconductor device, comprising:
providing a semiconductor substrate having predetermined source/drain regions;
performing an implantation process to form implanted regions in the predetermined source/drain regions;
performing an etching process to remove the implanted regions and form trenches; and
performing a selective epitaxial growth to fill epitaxial crystal comprising at least one of silicon, germanium, and carbon into the trenches.

### Claim 18 (depends on 17)

The method of claim 17 wherein a dopant selected from the atom or an ion of boron, germanium, arsenic, phosphorus, antimony, or xenon is used in the implantation process.

### Claim 19 (depends on 17)

The method of claim 17 wherein the implantation process comprises a preamorphizing implantation to amorphize the predetermined source/drain regions.

### Claim 20 (depends on 17)

The method of claim 17, after the implantation process, further comprising a step of annealing.

### Claim 21 (depends on 17)

The method of claim 17 wherein a profile of the source/drain regions is controlled by an implanting species, implanting dosage, implanting energy, implanting tilt angle, annealing temperature, or annealing time.

### Claim 22 (depends on 20)

The method of claim 20 wherein the annealing comprises rapid is thermal processing at a temperature between 1070° C. and 1100° C.

### Claim 23 (depends on 17)

The method of claim 17 wherein the etching process is a wet etching process.

### Claim 24 (depends on 23)

The method of claim 23 wherein a hot phosphoric acid solution is used as an etchant in the wet etching process.

### Claim 25 (depends on 17)

The method of claim 17 wherein the etching process is a dry etching process.

### Claim 26 (depends on 17)

The method of claim 17 wherein the epitaxial crystal further comprises a dopant.

### Claim 27

A method of manufacturing a MOS transistor, comprising:
providing a semiconductor substrate;
forming a gate structure on the semiconductor substrate;
performing an implantation process to form two implanted regions in the semiconductor substrate respectively adjacent to the gate structure;
performing an etching process to remove each implanted region and form a trench; and
performing a selective epitaxial growth to fill epitaxial crystal comprising at least one of silicon, carbon, and germanium into the trenches, thereby forming a source and a drain of the MOS transistor.

### Claim 28 (depends on 27)

The method of claim 27 wherein an oxide-nitride-oxide (ONO) offset spacer is formed on each sidewall of the gate structure, the implantation process is a tilt-angle implantation process and the trench is partly beneath the oxide-nitride-oxide offset spacer.

### Claim 29 (depends on 27)

The method of claim 27, after the implantation process, further comprising a step of annealing.

### Claim 30 (depends on 29)

The method of claim 29 wherein a profile of the source/drain of the MOS transistor is controlled by an implanting species, implanting dosage, implanting energy, implanting tilt angle, annealing temperature, or annealing time.

### Claim 31 (depends on 27)

The method of claim 27 wherein the etching process is a wet etching process.

### Claim 32 (depends on 31)

The method of claim 31 wherein a hot phosphoric acid solution is used as an etchant in the wet etching process.