# US 7,071,045 B2 · Process of manufacturing thin film transistor

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- Number: US 7,071,045 B2
- Document ID: US7071045B2
- Status: Granted
- Kind: B2
- Application number: 10/839,170
- Filed: 2004-05-06
- Published: 2005-11-10
- Granted: 2006-07-04
- Earliest claimed: 2004-05-06
- Assignees: Chunghwa Picture Tubes, Ltd.
- Inventors: Ying-Ming Wu; Yi-Tsai Hsu; Chin-Tzu Kao; Yung-Hsin Wu; Jui-chung Chang
- Web page: https://patentgrep.com/patent/US7071045B2

## CPC

- H10D 86/0231: {using masks, e.g. half-tone masks}
- H10D 30/0316: {of lateral bottom-gate TFTs comprising only a single gate}
- H10D 30/0321: {comprising silicon, e.g. amorphous silicon or polysilicon}
- H10D 86/40: characterised by multiple TFTs
- H10D 86/60: wherein the TFTs are in active matrices
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A process of producing a thin film transistor includes forming a gate line on a substrate by first exposure and development processes. A source electrode, a drain electrode and a semiconductor channel are formed by second exposure and development processes. An island-shaped transistor is formed by third exposure and development processes. A protection layer with a contact hole therein is formed by fourth exposure and development processes. A pixel electrode is formed by fifth exposure and development processes to connect to the contact hole.

## Claims

### Claim 1

A process of producing a thin film transistor, comprising:
sequentially forming a first metal layer and a first photoresist on a substrate;
patterning the first photoresist by exposure and development processes using a first photomask, and forming a gate line on the substrate by etching, and removing the first photoresist after exposure;
sequentially forming an insulator layer, a semiconductor layer, an ohmic contact layer, a second metal layer and a second photoresist layer on a gate line;
patterning the second photoresist by exposure and development processes using a second photoresist, and forming a source and a drain on the ohmic contact layer alter etching to form a semiconductor channel between the source and the drain, and removing the second photoresist after exposure;
forming a third photoresist layer on the substrate, wherein the substrate includes the source, the drain, the semiconductor channel and the semiconductor layer;
patterning the third photoresist layer by exposure and development processes using a third photomask, and forming an island-shaped transistor region after etching and removing the third photoresist;
sequentially forming a protection layer and a fourth photoresist layer on the substrate with the island-shaped transistor region therein;
patterning the fourth photoresist layer by exposure and development processes using a fourth photomask, and defining a contact hole in the protection layer by etching, and removing the fourth photoresist layer;
sequentially forming a pixel electrode and a fifth photoresist layer on the protection layer; and
patterning a fifth photoresist by exposure and development processes using a fifth photomask, and forming a pixel electrode by etching that connects to the drain via the contact hole, and removing the fifth photoresist layer.

### Claim 2 (depends on 1)

The process of claim 1, wherein the first metal layer is made of a material selected from the group consisting of aluminum, chromium and molybdenum.

### Claim 3 (depends on 1)

The process of claim 1, wherein the second metal layer is made of a material selected from the group consisting of aluminum, chromium and molybdenum.

### Claim 4 (depends on 1)

The process of claim 1, wherein the protection layer is made of silicon nitride or silicon dioxide.

### Claim 5 (depends on 1)

The process of claim 1, wherein the pixel electrode is made of transparent indium-tin-oxide (ITO).

### Claim 6 (depends on 1)

The process of claim 1, wherein the channel is formed by back channel etching (BCE).

### Claim 7 (depends on 1)

The process of claim 1, wherein the first metal layer is formed on the substrate by dry or wet etching.

### Claim 8 (depends on 1)

The process of claim 1, wherein the channel is formed by dry etching the ohmic contact layer through the semiconductor layer.

### Claim 9 (depends on 1)

The process of claim 1. wherein the contact hole of the protection layer is formed by dry etching, the contact hole being exposed through the drain electrode.

### Claim 10 (depends on 1)

The process of claim 1, wherein the pixel electrode is formed by wet etching.

### Claim 11 (depends on 1)

The process of claim 1, wherein the semiconductor layer is made of amorphous silicon.

### Claim 12 (depends on 1)

The process of claim 1, wherein the ohmic contact layer is an N type heavily doped silicon layer.