# US 7,071,043 B2 · Methods of forming a field effect transistor having source/drain material over insulative material

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- Number: US 7,071,043 B2
- Document ID: US7071043B2
- Status: Granted
- Kind: B2
- Application number: 10/222,326
- Filed: 2002-08-15
- Published: 2004-02-19
- Granted: 2006-07-04
- Earliest claimed: 2002-08-15
- Assignees: Micron Technology, Inc.
- Inventors: Sanh D. Tang; Michael P. Violette; Robert Burke
- Web page: https://patentgrep.com/patent/US7071043B2

## CPC

- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- G06K 19/0723: {the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs}
- G06K 19/0726: {the arrangement including a circuit for tuning the resonance frequency of an antenna on the record carrier}
- G06K 19/07771: {the record carrier comprising means for minimising adverse effects on the data communication capability of the record carrier, e.g. minimising Eddy currents induced in a proximate metal or otherwise electromagnetically interfering object}
- H10D 30/0225: {using an initial gate mask complementary to the prospective gate location, e.g. using dummy source and drain electrodes}
- H10D 30/0275: {forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions}
- H10D 30/608: {having non-planar bodies, e.g. having recessed gate electrodes}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 62/371: {Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/259: {Source or drain electrodes being self-aligned with the gate electrode and having bottom surfaces higher than the interface between the channel and the gate dielectric}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0172: {Manufacturing their gate conductors}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 90/1906: {Preparing SOI wafers}
- H10W 10/0143: {comprising concurrently refilling multiple trenches having different shapes or dimensions}
- H10W 10/0145: {of trenches having shapes other than rectangular or V-shape (H10W10/0143 takes precedence)}
- H10W 10/061: {using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G06K: GRAPHICAL DATA READING (image or video recognition or understanding G06V); PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

In one implementation, a method of forming a field effect transistor includes etching an opening into source/drain area of a semiconductor substrate. The opening has a base comprising semiconductive material. After the etching, insulative material is formed within the opening over the semiconductive material base. The insulative material less than completely fills the opening and has a substantially uniform thickness across the opening. Semiconductive source/drain material is formed within the opening over the insulative material within the opening. A transistor gate is provided operatively proximate the semiconductive source/drain material. Other aspects and implementations are contemplated.

## Claims

### Claim 1

A method of forming a field effect transistor comprising:
providing masking material over semiconductive material of a semiconductor substrate, the masking material masking at least a portion of a transistor channel area;
while the masking material masks at least a portion of the transistor channel area, forming a lightly doped drain region within a source/drain area of semiconductive material of the semiconductor substrate;
after forming the lightly doped drain region, etching an opening into the source/drain area of the semiconductor substrate, the opening having a base comprising semiconductive material;
after the etching, forming insulative material within the opening over the semiconductive material base, the insulative material less than completely filling the opening and having a substantially uniform thickness across the opening;
forming semiconductive source/drain material within the opening over the insulative material within the opening; and
after forming the lightly doped drain region, providing a transistor gate operatively proximate the semiconductive source/drain material.

### Claim 2 (depends on 1)

The method of claim 1 wherein the semiconductor substrate comprises bulk semiconductive material, the opening being etched into the bulk semiconductive material.

### Claim 3 (depends on 1)

The method of claim 1 wherein the method forms multiple field effect transistors, the opening being in the form of a channel spanning source/drain areas of a plurality of the field effect transistors.

### Claim 4 (depends on 1)

The method of claim 1 comprising etching two of said openings for the transistor, forming said insulative material within the two openings, and forming said semiconductive source/drain material within the two openings over the insulative material received therein; the transistor gate being provided operatively proximate and between the semiconductive source/drain material formed in the two openings.

### Claim 5 (depends on 1)

The method of claim 1 wherein forming the insulative material comprises depositing insulative material and etching it back.

### Claim 6 (depends on 1)

The method of claim 1 wherein forming the insulative material comprises depositing insulative material and etching it back in a blanket manner without using a photoresist mask during said etching.

### Claim 7 (depends on 1)

The method of claim 1 wherein forming the insulative material comprises depositing insulative material to overfill the opening, and etching it back to less than completely fill the opening.

### Claim 8 (depends on 1)

The method of claim 1 wherein the insulative material has a thickness no greater than 1000 Angstroms.

### Claim 9 (depends on 1)

The method of claim 1 wherein the insulative material has a thickness no greater than 600 Angstroms.

### Claim 10 (depends on 1)

The method of claim 1 wherein the insulative material comprises silicon dioxide.

### Claim 11 (depends on 1)

The method of claim 1 wherein the semiconductive source/drain material forms an elevated source/drain of the field effect transistor.

### Claim 12 (depends on 1)

The method of claim 1 wherein,
the semiconductor substrate comprises bulk semiconductive material, the opening being etched into the bulk semiconductive material; and
forming the insulative material comprises depositing insulative material to overfill the opening, and etching it back to less than completely fill the opening.

### Claim 13 (depends on 12)

The method of claim 12 wherein the insulative material has a thickness no greater than 1000 Angstroms.

### Claim 14 (depends on 12)

The method of claim 12 wherein the insulative material has a thickness no greater than 600 Angstroms.

### Claim 15 (depends on 12)

The method of claim 12 wherein the semiconductive source/drain material forms an elevated source/drain of the field effect transistor.

### Claim 16 (depends on 1)

The method of claim 1 wherein forming the lightly doped drain region comprises doping a region of semiconductive material of the semiconductor substrate, the opening being etched through said doped region of semiconductive material.

### Claim 17 (depends on 1)

The method of claim 1 wherein the transistor gate is provided after forming the semiconductive source/drain material within the opening.

### Claim 18 (depends on 1)

The method of claim 1 wherein at least some of the masking material is sacrificial.

### Claim 19 (depends on 1)

The method of claim 1 wherein all of the masking material is sacrificial and removed prior to providing the transistor gate.