# US 7,071,040 B2 · Method of fabricating thin film transistor > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,071,040 B2 - Document ID: US7071040B2 - Status: Granted - Kind: B2 - Application number: 10/639,478 - Filed: 2003-08-13 - Published: 2004-02-19 - Granted: 2006-07-04 - Earliest claimed: 2002-08-15 - Assignees: NEC Corporation - Inventors: Naoki Matsunaga; Kenji Sera - Web page: https://patentgrep.com/patent/US7071040B2 ## CPC - H10D 30/0314: {of lateral top-gate TFTs comprising only a single gate} - H10D 30/0316: {of lateral bottom-gate TFTs comprising only a single gate} - H10D 30/0321: {comprising silicon, e.g. amorphous silicon or polysilicon} - H10D 30/6731: {Top-gate only TFTs} - H10D 30/6732: {Bottom-gate only TFTs} - H10D 30/6737: {characterised by the electrode materials} - H10D 30/6743: {Silicon} - H10D 30/6745: {Polycrystalline or microcrystalline silicon} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A method of fabricating a thin film transistor including an electrically insulating substrate, a semiconductor layer formed on the substrate, and source and drain electrodes formed above source and drain regions formed in the semiconductor layer, the source and drain electrodes being composed of aluminum or aluminum alloy, the method including the steps of forming a gate electrode, implanting impurity ions into the semiconductor layer for forming the source and drain regions, forming an interlayer insulating film entirely over the substrate, forming contact holes throughout the interlayer insulating film such that the source and drain regions are exposed through the contact holes, forming an electrically conductive film composed of aluminum or aluminum alloy, in the contact holes for forming the source and drain electrodes, and thermally annealing the substrate at 275 to 350 degrees centigrade for 1.5 to 3 hours in inert atmosphere. ## Claims ### Claim 1 A method of fabricating a thin film transistor including an electrically insulating substrate, a semiconductor layer formed on said substrate, and source and drain electrodes formed above source and drain regions formed in said semiconductor layer, said source and drain electrodes being composed of aluminum or aluminum alloy, said method comprising the steps of: (a) forming a gate electrode electrically insulated from said semiconductor layer through a gate insulating film; (b) implanting ions of impurity having a predetermined electrical conductivity, into at least a part of said semiconductor layer for forming said source and drain regions; (c) forming an interlayer insulating film entirely over said substrate; (d) forming contact holes throughout said interlayer insulating film such that at least a part of said source and drain regions is exposed through said contact holes; (e) forming an electrically conductive film composed of aluminum or aluminum alloy, in said contact holes for forming said source and drain electrodes electrically connecting said source and drain regions through said contact holes; and (f) immediately after said step (e), thermally annealing said substrate at 275 to 350 degrees centigrade for 1.5 to 3 hours in inert atmosphere. ### Claim 2 (depends on 1) The method as set forth in claim 1, wherein said gate electrode is formed above said semiconductor layer in said step (a). ### Claim 3 (depends on 1) The method as set forth in claim 1, wherein said gate electrode is formed below said semiconductor layer in said step (a). ### Claim 4 (depends on 1) The method as set forth in claim 1, wherein said gate electrode is used as a mask in formation of said source and drain regions in said step (b). ### Claim 5 (depends on 1) The method as set forth in claim 1, wherein said ions are implanted twice into said semiconductor layer in said step (b) in different impurity concentrations such that the resultant source and drain regions have a lightly-doped drain (LDD) structure. ### Claim 6 (depends on 1) The method as set forth in claim 1, further comprising the step of (g) activating said semiconductor layer and applying hydrogen-plasma to said semiconductor layer, said step (g) being to be carried out between said steps (b) and (c). ### Claim 7 (depends on 1) The method as set forth in claim 1, wherein said interlayer insulating film is formed in said step (c) so as to have a multi-layered structure. ### Claim 8 (depends on 1) The method as set forth in claim 1, wherein said semiconductor layer is comprised of a polysilicon film. ### Claim 9 (depends on 1) The method as set forth in claim 1, wherein said substrate is thermally annealed in said step (f) in a nitrogen, arson, neon or helium atmosphere. ### Claim 10 A method of fabricating a thin film transistor including an electrically insulating substrate, a semiconductor layer formed on said substrate, and source and drain electrodes formed above source and drain regions formed in said semiconductor layer, said source and drain electrodes being composed of aluminum or aluminum alloy, said method comprising the steps of: (a) forming a gate electrode electrically insulated from said semiconductor layer through a gate insulating film; (b) implanting ions of impurity having a predetermined electrical conductivity, into at least a part of said semiconductor layer for forming said source and drain regions; (c) forming an interlayer insulating film entirely over said substrate; (d) forming contact holes throughout said interlayer insulating film such that at least a part of said source and drain regions is exposed through said contact holes; (e) forming an electrically conductive film composed of aluminum or aluminum alloy, in said contact holes for forming said source and drain electrodes electrically connecting said source and drain regions through said contact holes; and (f) immediately after said step (e), thermally annealing said substrate in an inert atmosphere. ### Claim 11 (depends on 10) The method as set forth in claim 10, wherein said annealing is performed at least 275 degrees centigrade. ### Claim 12 (depends on 10) The method as set forth in claim 10, wherein said annealing is performed at 275 to 350 degrees centigrade. ### Claim 13 (depends on 10) The method as set forth in claim 10, wherein said annealing is performed for at least 1.5 hours. ### Claim 14 (depends on 10) The method as set forth in claim 10, wherein said annealing is performed for 1.5 to 3 hours. ### Claim 15 (depends on 10) The method as set forth in claim 10, further comprising the step of (g) forming a pixel electrode which electrically connects said source electrode to said drain electrode, said step (g) being to be carried out after said step (f). ### Claim 16 (depends on 15) The method as set forth in claim 15, further comprising the step of (h) forming a planarization film and a passivation film over the resultant device of claim 15, said step (h) being to be carried out after said step (g). ### Claim 17 (depends on 10) The method as set forth in claim 10, wherein said gate electrode is formed above said semiconductor layer in said step (a). ### Claim 18 (depends on 10) The method as set forth in claim 10, wherein said gate electrode is formed below said semiconductor layer in said step (a). ### Claim 19 (depends on 10) The method as set forth in claim 10, wherein said interlayer insulating film is formed in said step (c) so as to have a multi-layered structure.