# US 7,071,020 B2 · Method of forming an elevated photodiode in an image sensor

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- Number: US 7,071,020 B2
- Document ID: US7071020B2
- Status: Granted
- Kind: B2
- Application number: 11/126,343
- Filed: 2005-05-11
- Published: 2005-09-22
- Granted: 2006-07-04
- Earliest claimed: 2003-05-23
- Assignees: Micron Technology, Inc.
- Inventors: Sungkwon Hong
- Web page: https://patentgrep.com/patent/US7071020B2

## CPC

- H10F 39/805: {Coatings}
- H10F 39/014: {of CMOS image sensors}
- H10F 39/803: {Pixels having integrated switching, control, storage or amplification elements}
- H10F 39/811: {Interconnections}
- H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION

## Abstract

The invention provides an elevated photodiode for image sensors and methods of formation of the photodiode. Elevated photodiodes permit a decrease in size requirements for pixel sensor cells while reducing leakage, image lag and barrier problems typically associated with conventional photodiodes.

## Claims

### Claim 1

A method of forming a pixel sensor cell comprising:
forming a blocking layer on a first substrate layer and over at least one transistor gate;
forming a plurality of openings in the blocking layer;
growing an epitaxial layer of silicon in said plurality of openings;
etching said blocking layer after growing the epitaxial layer to form a sidewall on said at least one transistor gate.

### Claim 2 (depends on 1)

The method according to claim 1 wherein said blocking layer is silicon dioxide.

### Claim 3 (depends on 1)

The method according to claim 1 wherein said epitaxial layer in said plurality of openings is grown to a thickness of about 1000 §.

### Claim 4 (depends on 1)

The method according to claim 1 wherein at least one of said plurality of openings is formed over a region where a photoconversion device is to be formed.

### Claim 5 (depends on 1)

The method according to claim 1 wherein at least one of said plurality of openings is formed over a region where a source/drain region for a transistor having said at least one transistor gate is to be formed.

### Claim 6 (depends on 1)

The method according to claim 1 further comprising etching said blocking layer to form sidewalls on a plurality of transistor gates.