Micro structure with interlock configuration
AssigneeYamaha Corporation
InventorTamito Suzuki
Life of this patent
Estimating the term…
Abstract
A micro structure has: a semiconductor substrate; an insulating film having a via hole and formed on the semiconductor substrate; an interlock structure formed on a side wall of the via hole and having a retracted portion and a protruded portion above the retracted portion; a conductive member having at one end a connection portion formed burying the via hole and an extension portion continuous with the connection portion and extending along a direction parallel to a surface of the semiconductor substrate.
Claims13
A micro structure manufacture method comprising the steps of:
- (a) forming an insulating film on a semiconductor substrate, said insulating film including a lower layer and an upper layer;
- (b) forming a sacrificial film on said insulating film;
- (c) forming a via hole through said sacrificial film and said insulating film;
- (d) forming an interlock mechanism on a side wall of said via hole, said interlock mechanism including a retracted portion and a protruded portion above said retracted portion;
- (e) depositing a conductive film on said sacrificial film, said conductive film burying said via hole;
- and
- (f) patterning said conductive film.
A micro structure manufacture method comprising the steps of:
- (a) forming an insulating film above a principal surface of an underlying substrate;
- (b) forming a via hole through said insulating film, said via hole reaching said underlying substrate;
- (c) depositing a doped silicon layer in a thickness range of 1 to 15 μm on said insulating film, said doped silicon layer burying said via hole and doped with impurities in an impurity/silicon mol ratio range of 0.05 to 0.1;
- (d) annealing said silicon layer to relax stress;
- and
- (e) before or after said annealing, patterning said silicon layer to have a predetermined electrode or wiring pattern.
A dry etching method comprising the steps of:
- (a) forming a silicon layer having a thickness of 1 to 15 μm above a substrate having an insulating principal surface;
- (b) forming an organic material resist pattern on said silicon layer, said organic material resist pattern having a thickness of 1 to 1.5 times a thickness of said silicon layer;
- (c) anisotropically etching said silicon layer down to the insulating principal surface of said substrate by plasma etching while side wall protective films are formed by using etching gas which contains chlorine, oxygen and fluorine and said resist pattern as a mask;
- (d) over-etching said silicon layer by plasma etching using etching gas which contains chlorine and oxygen and does not contain fluorine and said resist pattern as a mask;
- and
- (e) removing a remaining portion of said resist pattern and a remaining portion of said side wall protective film.
Dependencies are inferred from the claim text.