US 7,071,009 B2 · MRAM arrays with reduced bit line resistance and method to make the same

Abstract

Improved MRAM arrays and a method of forming the same are disclosed in which a bit line has thinner portions formed over MTJs and thicker portions therebetween. Bottom electrodes are formed in a first insulation layer on a substrate and then MTJs and a coplanar second insulation layer are formed thereon. After a second conductive layer comprised of lower metal lines is formed above the MTJs, a trench is formed in a stack of insulation layers above portions of the lower metal lines. A barrier layer and upper metal layer are sequentially deposited and then planarized to form a filled trench that effectively increases a bit line thickness. The lower metal layer is a thin bit line in regions over MTJs. The method may also comprise forming word lines on an insulation layer that are aligned over the MTJs and perpendicular to the bit lines.

Claims26

Dependent claims

A method of fabricating an MRAM array on a substrate, comprising:

(a) forming a first conductive layer comprised of a plurality of sectioned first lines on a substrate;
(b) forming an array of magnetic tunnel junctions (MTJs) on the first conductive layer;
and
(c) forming a second conductive layer comprised of a plurality of parallel second lines on said MTJs wherein an MTJ is formed at each location where a second line crosses over a sectioned first line and wherein said second lines have thinner and thicker regions, said thicker regions are not formed above an MTJ or adjacent to an MTJ.

1 more element

A method for fabricating an MRAM array on an MRAM chip, comprising:

(a) forming a first conductive layer comprised of a plurality of sectioned first lines in a second insulation layer on a substrate that has an upper first insulation layer;
(b) forming an array of MTJs on said first conductive layer and forming a planar third insulation layer on said second insulation layer and first conductive layer wherein said third insulation layer is coplanar with said MTJs;
(c) forming a second conductive layer which is a lower metal layer comprised of a plurality of parallel second lines having a first thickness and a first width on said MTJs and third insulation layer, said second lines are formed in and are coplanar with a dielectric layer;
(d) forming a fourth insulation layer on said second conductive layer and dielectric layer and forming openings over portions of said second lines that are not above said MTJs;
(e) forming a fifth insulation layer on said fourth insulation layer and second lines and forming a pattern comprised of a plurality of first trenches having sidewalls and bottoms on said fourth insulation layer and above said MTJs and a plurality of second trenches having sidewalls and bottoms on portions of said second lines that are not above said MTJs;
(f) depositing a conformal diffusion barrier layer on the sidewalls and bottoms of said first trenches and second trenches and depositing an upper metal layer on said diffusion barrier layer that fills said first and second trenches;
and
(g) planarizing said diffusion barrier layer and upper metal layer to be coplanar with said fifth insulation layer thereby forming parallel third lines in said first trenches, and thicker regions of said second lines where a second trench is formed on said lower metal layer wherein a lower metal layer, an overlying diffusion barrier layer, and an upper metal layer on the diffusion barrier layer form a thicker region that has a second thickness greater than said first thickness.

5 more elements

Dependencies are inferred from the claim text.

MRAM arrays with reduced bit line resistance and method to make the same

Life of this patent

MRAM arrays with reduced bit line resistance and method to make the same

Life of this patent

Abstract

Claims26