Inter-procedure global register allocation method

A computer-readable medium storing instructions adapted to be executed by a processor, the instructions comprising:

• identifying a plurality of variables from an acyclic call graph having a plurality of functions;
• creating a plurality of virtual registers by assigning each of the plurality of variables to at least one virtual register;
• constructing an interference graph based on the plurality of virtual registers, wherein constructing the interference graph includes sorting the acyclic call graph into a doubly-linked list;
• coloring the interference graph with a plurality of physical registers;
• and
• if the interference graph is not colorable, spilling at least one virtual register from the interference graph.

A system for optimizing processor register allocation, comprising:

• a target system including a memory and at least one processor having a plurality physical registers;
• and
• a developer system, coupled to the target system, including:
• a memory, and
• at least one processor adapted to:
• identify a plurality of variables from an acyclic call graph having a plurality of functions,
• create a plurality of virtual registers by assigning each of the plurality of variables to at least one virtual register;
• construct an interference graph based on the plurality of virtual registers, wherein to construct of the interference graph, the one processor is adapted to sort the acyclic call graph into a doubly-linked list,
• color the interference graph with at least one of the plurality of physical registers, and
• if the interference graph is not colorable, spill at least one virtual register from the interference graph.