Method and apparatus for generating a solid state circuit layout with in-design variability associated to the setting of analog signal processing parameters, and an integrated circuit design and an integrated circuit produced by applying such method

An apparatus for generating a Solid State Integrated Circuit Layout comprising:

• a receiver that is configured to receive an intended plurality of specified functions,
• a translator that is configured to translate the plurality of specified functions into a plurality of circuitry representations,
• a converter that is configured to convert the plurality of circuitry representations into circuit items of an overall circuit, and
• a configuring element that is configured to configure first interfaces between interacting circuit items within the overall circuit and second interfaces between further such circuit items and an external interface in accordance with predetermined interface specifications,
• an assignor that is configured to, in a situation wherein various such circuit items represent respective analog and/or steppable values of a parameter to be specified on the basis of a circuit item:
• assign a parameter to a single such circuit item to be realized as a building block, and
• assign a sufficient amount of in-design resizability space to the building block in accordance with a prespecified redefinability value range for the parameter.

A method for generating a Solid State Integrated Circuit Layout comprising:

• specifying an intended plurality of functions,
• translating the plurality of functions into various circuitry representations,
• converting the circuitry representations into circuit items of an overall circuit,
• configuring first interfaces between interacting circuit items within the overall circuit and second interfaces between further such circuit items and an external interface in accordance with predetermined interface specifications, and
• generating the integrated circuit layout in a top-down design flow, wherein the following design levels are executed:
• a. specifying an overall circuit functionality and key parameter trade-offs,
• b. detailing the overall circuit functionality into multiple library layout building blocks, wherein one or more of the library blocks includes a sufficient amount of in-design resizability space in accordance with a prespecified redefinability value range for reprogrammable parameter values.
• c. (re)-assigning to the one or more library blocks various reprogrammable parameter values.
• d. testing the overall circuit to provide a first tested performance,
• e. returning to step c, if the first tested performance does not satisfy a target performance,
• f. introducing parasitic values associated to the overall circuit as specified,
• g. testing the overall circuit with the parasitic values to provide a second tested performance.
• h. returning to step c, if the second tested performance does not satisfy the target performance.