Various methods and apparatuses to preserve a logic state for a volatile latch circuit
AssigneeVirage Logic Corporation
InventorsGene T. Sluss, Deepak D. Sherlekar, Tushar R. Gheewala
Life of this patent
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Abstract
Various methods and apparatuses are described in which a volatile latch circuit. The volatile latch circuit may have a master latch sub circuit coupled to a slave latch sub circuit. The slave latch sub circuit maintains the logic state stored by the volatile latch circuit. The slave sub circuit may connect to a first power trace that continuously provides a first voltage potential to the slave latch sub circuit even during a sleep mode. The master latch sub circuit may connect to a second power trace that provides a second voltage potential to the master latch sub circuit that is switchably turned off during the sleep mode.
Claims27
A machine readable storage medium that stores data representing an apparatus, which when manipulated by a machine creates the representation of the apparatus, comprising:
- a volatile latch circuit having a master latch sub circuit coupled to a slave latch sub circuit, wherein the slave latch sub circuit maintains a logic state stored by the volatile latch circuit, and the slave sub circuit connects to a first power trace that continuously provides a first voltage potential to the slave latch sub circuit even during a sleep mode, the master latch sub circuit connects to a second power trace that provides a second voltage potential to the master latch sub circuit that is switchably turned off during the sleep mode.
A machine readable storage medium that stores data representing an apparatus, which when manipulated by a machine creates the representation of the apparatus, comprising:
- an integrated circuit containing
- a volatile latch circuit having a master latch sub circuit and a slave latch sub circuit to store and maintain a logic state, wherein the volatile latch circuit is configured to operate in two or more modes of operation including a sleep mode, wherein the volatile latch circuit having a plurality of transistors is contained in a first macro cell, wherein a first power trace to supply a VDD voltage potential, a second power trace to supply a second voltage potential, and a third power trace to supply a third voltage potential, wherein the power traces connect to the volatile latch circuit, the first power trace connects to a source terminal of a first set of one or more transistors in the first macro cell, and the third power trace connects to a source terminal of a second set of one or more transistors in the macro cell to preserve the logic state of the volatile latch circuit during the sleep mode.
A machine readable storage medium that stores data representing an apparatus, which when manipulated by a machine creates the representation of the apparatus, comprising:
- an integrated circuit containing
- a volatile latch circuit to store and maintain a logic value, wherein the volatile latch circuit is configured to operate in two or more modes of operation, wherein a first power trace to supply a VSS voltage potential to a source terminal of a first transistor, a second power trace to supply a VDD voltage potential to a source terminal of a second transistor, and a third power trace to supply a third voltage potential to a well substrate of the second transistor to operate the volatile latch circuit in three or more power consumption modes as well as three or more performance modes.
A method, comprising:
- routing a first power trace to carry a first voltage potential along a row of macro cells;
- routing a second power trace to carry a second voltage potential along the row of macro cells;
- routing a third power trace to carry a third voltage potential along the row of macro cells;
- routing the row of macro cells on a chip in the same direction as the routed power traces;
- connecting a first macro cell to the first power trace;
- connecting a second macro cell to the second power trace but not the first power trace, wherein the second macro cell is adjacent to the first macro cell and in the same set of rows as the first macro cell;
- and
- controlling whether power is applied to the first macro cell by changing the first voltage potential from the first power trace.
Dependencies are inferred from the claim text.