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US 7,069,485 B2Granted
Reading data from a memory with a memory access controller
AssigneeTexas Instruments Incorporated
InventorsLee Doyle Whetsel, Jr., Benjamin H. Ashmore, Jr.
Life of this patent
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Abstract
A serial scan path communication architecture includes a plurality of circuits (30), some of which may include a memory (36). A memory access controller (38) is included in circuits with a memory (36) such that serial data may be written to and written from the memories without having to repetitively cycle through multiple TAP read or write operations operations.
Claims11
A method of reading words of data from a device coupled to a register, which is in series with a serial data output, comprising:
- A. loading a controller with control data to provide read data control signals to the register and the device;
- B. transferring a word of data in parallel from the device into the register in response to the control signals;
- C. shifting data from the register in series to the serial data output in response to the control signals;
- and
- D. repeating steps B. and C. for additional words of data after the last data bit of the previous word of data is shifted out of the register without loading the controller with additional control data.
2 more elements
A process of reading words of data from a memory comprising:
- A. loading a control register with control data to select a memory access controller;
- B. transferring a word of data in parallel from the memory into a data register in response to first control signals in a first state;
- C. shifting data from the data register in series in response to first control signals in a second state;
- D. transferring a word of data in parallel from the memory into the data register after the last data bit of the previous word of data is shifted out of the data register in response to memory access control signals from the memory access controller while maintaining the first control signals in the second state;
- and
- E. shifting data from the data register in series in response to memory access control signals from the memory access controller while maintaining the first control signals in the second state.
3 more elements
Dependencies are inferred from the claim text.