ROM error-correction control

A fuse-controlled error-correction control system for a ROM, comprising:

• a defective memory-cell address detector circuit (CMP) that compares input address signals for the ROM to a plurality of fuse-controlled preset static addresses of a predetermined corresponding plurality of defective memory cells of the ROM and that provides a plurality of corresponding address-hit output signals (ADDHIT), which indicate the occurrence of one of the input address signals corresponding to one of the fuse-controlled preset static addresses of one of the predetermined defective memory cells;
• an (AOUT) circuit that receives the address-hit output signals ADDHIT signal and that provides a corresponding bit-reversal output signal (REV) for each defective memory cell;
• and
• a plurality of data output buffers that receives data bits from memory cells of the ROM, including bits from said predetermined defective memory cells, each of said plurality of data output buffers having an output terminal coupled to a data output terminal of the ROM, each of said data output buffers having an output-reversal control terminal for receiving one of the bit-reversal output signals REV that reverses the sense of the data signal corresponding to one of the predetermined defective memory cell at the output terminal of the data output buffer when the address of one of the defective memory cell is detected by the defective memory-cell address detector circuit CMP.

A method of controlling error-correction for a ROM, comprising the steps of:

• comparing input address signals for the ROM to a fuse-controlled preset static address of a predetermined defective memory cell of the ROM;
• providing an address-hit output signal (ADDHIT), which indicates the occurrence of input address signals corresponding to said fuse-controlled preset static address of said predetermined defective memory cell;
• providing a corresponding bit-reversal output signal (REV) in response to the address-hit output signal ADDHIT;
• in response to the bit-reversal output signal (REV), reversing the sense of the data signal corresponding to the predetermined defective memory cell at the output terminal of a data output buffer when the address of the defective memory cell is detected by the defective memory-cell address detector circuit CMP.