Methods and arrangements to enhance a bus

A system, comprising:

• a controller to generate a test signal in response to coupling a device with a bus;
• a bridge coupled with the controller to transmit the test signal on the bus;
• a device interface to couple the device to the bus and receive a bus signal from the bus and, coupled with the controller and the bridge, to determine an error signal based upon the test signal and the bus signal;
• and
• a processor coupled with the bridge to communicate with the device;
• wherein the device interface comprises comparison circuitry to generate the error signal based upon comparison of a bit of a comparison signal against a bit of the bus signal, wherein the comparison signal is a bus signal anticipated to be received via the bus in response to transmission of the test signal.

A machine-readable medium containing instructions, which when executed by a machine, cause said machine to perform operations, comprising:

• determining a test signal to transmit on a bus in response to coupling a device with a device interface for the bus;
• interpreting an error signal generated in response to transmission of the test signal to determine a fault associated with the bus;
• and
• isolating the device from the bus when an interpretation of the error signal indicates that the fault is associated with the device;
• wherein interpreting an error signal comprises interpreting the error signal based upon an interpretation of another error signal.

A method, comprising:

• determining a test signal in response to coupling a device with a device interface for a bus;
• transmitting the test signal on the bus;
• determining a bus signal at the device interface after transmitting the test signal;
• and
• generating an error signal based upon a difference between the bus signal and a comparison signal anticipated as a response to transmitting the test signal on the bus;
• wherein generating an error signal comprises combining the bus signal and the comparison signal with XOR logic.