Method and apparatus to release a serial bus from a suspended state

In a serial bus of the type in which cycles of a normally applied clock signal occur in time synchronism with data bits of a data signal when performing a transaction communicated between two bus controllers of the serial bus, an improvement for releasing one bus controller from a stuck condition occurring during a transaction, the improvement comprising:

• an artificial clock signal generator connected to a bus controller and operative upon activation to generate cycles of the artificial clock signal and to apply the cycles of the artificial clock signal to the stuck bus controller in lace of the normally applied clock signal;
• and
• detection circuitry connected to a bus controller and receptive of the data bits of the data signal communicated between the two bus controllers during the transaction, the detection circuitry detecting an absence of chance in a logical level of the data signal to identify the stuck bus condition, the detection circuitry connected to the artificial clock signal generator to activate the artificial clock signal generator to generate the cycles of the artificial clock signal in response to detecting the stuck bus condition, and wherein:
• the detection circuitry comprises a microcontroller connected to the bus controller which executes programmed functionality to sample the level of the data signal to detect the absence of change in the logical level of the data signal;
• and
• the artificial clock signal generator also comprises the microcontroller which also executes programmed functionality to deliver the cycles of the artificial clock signal.

In a serial bus of the type in which cycles of a normally applied clock signal occur in time synchronism with data bits of a data signal when performing a transaction communicated between two bus controllers of the serial bus, an improvement for releasing one bus controller from a stuck condition occurring during a transaction, the improvement comprising:

• an artificial clock signal generator connected to a bus controller and operative upon activation to generate cycles of the artificial clock signal and to apply the cycles of the artificial clock signal to the stuck bus controller in place of the normally applied clock signal;
• and
• detection circuitry connected to a bus controller and receptive of the data bits of the data signal communicated between the two bus controllers during the transaction, the detection circuitry detecting an absence of change in a logical level of the data signal to identify the stuck bus condition, the detection circuitry connected to the artificial clock signal generator to activate the artificial clock signal generator to generate the cycles of the artificial clock signal in response to detecting the stuck bus condition, and wherein:
• the detection circuitry comprises programmed logic circuitry connected to the bus controller which executes logic functionality to sample the level of the data signal to detect the absence of change in the logical level of the data signal;
• and
• the artificial clock signal generator responds to the programmed logic circuitry detecting the absence of change in the logical level of the data signal to deliver the cycles of the artificial clock signal.