Hybrid parallel/serial bus interface
AssigneeInterDigital Technology Corporation
InventorsJoseph Gredone, Alfred Stufflet, Timothy A. Axness
Life of this patent
Estimating the term…
Abstract
A hybrid serial/parallel bus interface has a data block demultiplexing device. The data block demultiplexing device has an input configured to receive a data block and demultiplexes the data block into a plurality of nibbles. For each nibble, a parallel to serial converter converts the nibble into serial data. A line transfers each nibble's serial data. A serial to parallel converter converts each nibble's serial data to recover that nibble. A data block reconstruction device combines the recovered nibbles into the data block.
Claims45
A hybrid serial to parallel bus interface comprising:
- a data block demultiplexing device having an input configured to receive a data block and demultiplexing the data block into a plurality of nibbles, each nibble having a plurality of bits;
- for each nibble:
- a parallel to serial converter for converting that nibble into serial data;
- a line for transferring that nibble serial data;
- and a serial to parallel converter for converting that nibble serial data to recover that nibble;
- and a data block reconstruction device for combining the recovered nibbles into the data block.
A hybrid serial to parallel bus interface comprising:
- means having an input configured to receive a data block for demultiplexing the data block into a plurality of nibbles, each nibble having a plurality of bits;
- for each nibble:
- means for converting that nibble into serial data;
- a line for transferring that nibble serial data;
- and means for converting that nibble serial data to recover that nibble;
- and means for combining the recovered nibbles into the data block.
A method for transferring data, the method comprising:
- providing a data block;
- demultiplexing the data block into a plurality of nibbles, each nibble having a plurality of bits;
- for each nibble:
- converting that nibble into serial data;
- providing a line and transferring the nibble serial data over the line;
- converting that nibble serial data into parallel data to recover that nibble;
- and combining the recovered nibbles into the data block.
A method for transferring a data block through an interface connecting a first node to a second node, the method comprising:
- demultiplexing the data block into m sets of n bits;
- adding a start bit to each of the m sets, the m start bits collectively representing one of a particular mathematical function or destination;
- transferring from the first node each of the m sets over a separate line;
- receiving at the second node each of the transferred m sets;
- and utilizing the received in sets in accordance with the m start bits.
A method for transferring a data block through an interface connecting a first node to a second node, the method comprising:
- demultiplexing the data block into m sets of n bits:
- adding a start bit to each of the m sets, the m start bits collectively representing both a particular mathematical function and destination;
- transferring from the first node each of the m sets over a separate line;
- receiving at the second node each of the transferred m sets;
- and utilizing the received m sets in accordance with the m start bits.
A hybrid serial to parallel bus interface for transferring data from a first node to a second node, the interface comprising:
- a data block demultiplexing device for demultiplexing a data block from the first node into m sets of n bits and for adding a start bit to each of the m sets, the m start bits collectively representing one of a particular mathematical function or destination;
- for each of the m sets, a separate line for transferring that set of the m sets from the first node to the second node;
- a data block reconstruction device for receiving the m sets, for combining the m sets into the data block and for utilizing the m sets in accordance with the m start bits.
A hybrid serial to parallel bus interface for transferring data from a first node to a second node, the interface comprising:
- a data block demultiplexing device for demultiplexing a data block from the first node into m sets of n bits and for adding a start bit to each of the m sets, the m start bits collectively representing both a particular mathematical function and destination;
- for each of the m sets, a separate line for transferring that set of the m sets from the first node to the second node;
- and a data block reconstruction device for receiving the m sets, for combining the m sets into the data block and for utilizing the m sets in accordance with the m start bits.
A hybrid serial to parallel bus interface for transferring data from a first node to a second node, the interface comprising:
- means for demultiplexing a data block into m sets of n bits;
- means for adding a start bit to each of the m sets, the m start bits collectively representing one of a particular mathematical function or destination;
- means for transferring from the first node each of the m sets over a separate line;
- means for receiving at the second node each of the transferred m sets;
- and means for utilizing the received m sets in accordance with the m start bits.
A hybrid serial to parallel bus interface for transferring data from a first node to a second node, the interface comprising:
- means for demultiplexing a data block into m sets of n bits:
- means for adding a start bit to each of the m sets, the m start bits collectively representing both a particular mathematical function and destination;
- means for transferring from the first node each of the m sets over a separate line;
- means for receiving at the second node each of the transferred m sets:
- and means for utilizing the received m sets in accordance with the m start bits.
A hybrid serial to parallel bus interface for use in a synchronous system, the synchronous system having an associated clock, the bus interface comprising:
- a data block demultiplexing device having an input configured to receive a data block and demultiplexing the data block into a plurality of nibbles, each nibble having a plurality of bits;
- an even and odd set of parallel to serial (P/S) converters, each set of P/S converters receiving the nibbles synchronous with a clock rate of the clock, and for converting the nibbles into a serial data;
- a first set of i multiplexers for transferring the even P/S converters set serial data on a positive edge of the clock over i lines and the odd P/S converters set serial data on a negative edge of the clock over i lines;
- a second set of i demultiplexers for receiving the even and odd transferred serial data and sending the even received serial data to an ever buffer and the odd serial data to an odd buffer;
- an even and odd set of serial to parallel (S/P) converters, the even set of S/P converters for converting the even received serial data to even parallel data and outputting the even parallel data synchronous with the clock;
- and the odd set of S/P converters for converting the odd received serial data to odd parallel data and outputting the odd parallel data synchronous with the clock;
- and a data block reconstruction device for combining the even and odd parallel data as the data block.
A method for determining a number of i bus connections required to transfer block data over a bus, each block of the block data having N number of bits, the method comprising:
- determining a maximum latency allowed for transfer of the block data;
- determining a minimum number of connections required to transfer the data block with the maximum latency;
- and determining i with i being a value at least the minimum number of required connections.
A system using a bi-directional serial to parallel bus interface comprising:
- a plurality of lines for transferring data blocks, the plurality of lines numbering less than a number of bits of each data block;
- a first node sending first data blocks to a second node over the plurality of lines, the first node capable of demultiplexing the data block into a plurality of first nibbles, the plurality of first nibbles numbering a same number as the plurality of lines, each nibble having a plurality of bits;
- and the second node sending second data blocks to the first node over the plurality of lines, the second node capable of demultiplexing the data block into a plurality of second nibbles, the plurality of second nibbles numbering a same number as the plurality of lines, each nibble having a plurality of bits.
Dependencies are inferred from the claim text.