Closed-loop, supply-adjusted RAM memory circuit
AssigneeNational Semiconductor Corporation
InventorsWai Cheong Chan, James Thomas Doyle, Pavel Poplevine, Murali Krishna Varadarajula, Hsing-Chien Roy Liu, Gordon Mortensen
Life of this patent
Estimating the term…
Abstract
The supply voltage of a memory system is adjusted in response to changes in the frequency of the clock signal. The memory system measures a time from when data becomes valid on the output of a memory to the next clock edge to determine a timing value. When the clock frequency changes from a first frequency to a second frequency, the timing value changes from a first value to a second value. The magnitude of the supply voltage is changed to return the timing value to the first value.
Claims29
A memory system comprising:
- a memory connected to a supply voltage, the memory having a clock input that receives a clock signal, a data input that receives to-be-stored data, and a data output that outputs a data output signal that outputs stored memory data;
- a time slack detector circuit that receives a sample signal and a launch signal, and outputs timing data defined by the sample and launch signals, the timing data having a first value when the clock signal has a first frequency, and a second value when the clock signal has a second frequency;
- and
- a control circuit connected to the memory and the time slack detector circuit, the control circuit generating the launch signal in response to the data output signal, and the sample signal in response to the launch signal, the control circuit detecting a change in the timing data and, in response to the change, outputting a signal that adjusts a magnitude of the supply voltage.
A method of adjusting a magnitude of a supply voltage provided to a circuit, the circuit having a memory, the memory having a memory clock input that receives a clock signal, a data input that receives to-be-stored data, a supply voltage input, and a memory data output that outputs memory data, the method comprising:
- outputting a timing value, the timing value having a first value when the clock signal has a first frequency, and a second value when the clock signal has a second frequency, the timing value representing a time measured from when data becomes valid on the memory data output to a next edge of the clock signal;
- detecting a change in the timing value;
- and
- outputting a signal that adjusts a magnitude of the supply voltage in response to the change.
Dependencies are inferred from the claim text.