US 7,069,423 B2 · Microcomputer

Abstract

A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.

Claims9

Dependent claims

A single chip microprocessor comprising:

a first processing unit including an instruction register and an instruction decoder;
a second processing unit;
first, second and third address buses coupled to the first processing unit;
first, second and third data buses;
a first memory coupled to the first and second address buses and to the first and second data buses;
and
a second memory coupled to the first and third address buses and to the first and third data buses;
wherein the instruction decoder decodes an instruction fetched in the instruction register and provides control signals to the second processing unit according to the decoding of the instruction.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application

10/201,402Filed 22 Jul 2002 · continuation

Priority

JP 7-1329062 May 1995

Published

US 2002/0184472 A15 Dec 2002

Granted

27 Jun 2006

Term ends

Not estimatedThe source records don’t support an estimate.

Classification16 codes

G06F 9/3893
Using a plurality of independent parallel functional units: controlled in tandem, e.g. multiplier-accumulator
G06F 9/3001
To perform operations on data operands: arithmetic instructions
G06F 9/30043
To perform operations on memory: lOAD or STORE instructions; Clear instruction
G06F 9/3013
Organisation of register space, e.g. banked or distributed register file: according to data content, e.g. floating-point registers, address registers

Family

Application08/630,320Parent of this continuation · filed 10 Apr 1996

Application09/229,147Parent of this continuation · filed 11 Jan 1999

US 2002/0184472 A1Pre-grant publication · published 5 Dec 2002

US 6,434,690 B1Parent of this continuation

US 5,867,726 AParent of this continuation

US 7,069,423 B2This patent

From the US filing history. Foreign family members aren’t listed.

Microcomputer

Life of this patent

Microcomputer

Life of this patent

Abstract

Claims9