Side tables annotating an instruction stream

A method, comprising the steps of:

• as part of the basic instruction cycle of executing an instruction of a non-supervisor mode program executing on a computer, consulting a table, the table having entries that are indexed by the address within an address space of instructions executed, entries of the table containing attributes of instructions whose addresses index to the respective table entries;
• and
• controlling an architecturally-visible data manipulation behavior or control transfer behavior of the instruction based at least in part on a content of a table entry indexed by the address of the instruction.

A microprocessor chip, comprising:

• instruction pipeline circuitry;
• table lookup circuitry designed to index into a table by a memory address of a memory reference arising during execution of an architecturally-defined instruction, and to retrieve a table entry corresponding to the address, the table entry being distinct from the memory referenced by the memory reference;
• the instruction pipeline circuitry being responsive to the contents of the table entry to alter a manipulation of data or control transfer behavior of the instruction in a manner incompatible with the architectural definition of the instruction in the instruction's native architecture.

A microprocessor chip, comprising:

• instruction pipeline circuitry;
• and
• interrupt circuitry cooperatively designed with the instruction pipeline circuitry to trigger a synchronous interrupt on execution of an instruction of a process based at least in part on a memory state of the computer and the address of the instruction, wherein the architectural definition of the instruction in the instruction's native architecture does not call for an interrupt.

A method, comprising the steps of:

• as an integral part of processing an instruction in instruction pipeline circuitry of a computer, consulting a lookup structure of entries, entries of the lookup structure corresponding to address ranges translated by address translation circuitry, and the entries describe a likelihood of the existence of an alternate coding of instructions located in the respective corresponding address ranges.

A method, comprising the steps of:

• as an integral part of processing an instruction in instruction pipeline circuitry of a computer, consulting a lookup structure of entries, each entry corresponding to an address range translated by address translation circuitry, and describing a likelihood of the existence of an alternate coding of instructions located in the respective corresponding address range;
• and
• as a result of the consulting, changing an instruction set architecture under which instructions are interpreted by the computer.

A method, comprising the steps of:

• on execution of an instruction of a process in a computer, triggering a synchronous interrupt based at least in part on a memory state of the computer and the address of the instruction, wherein the architectural definition of the instruction in the instruction's native architecture does not call for an interrupt.

A method, comprising the steps of:

• as part of the basic instruction cycle of executing an architecturally-defined instruction of a non-supervisor mode program executing on a computer, retrieving an entry from a table, the table entry being indexed by the address of a memory reference arising during execution of the architecturally-defined instruction, the table entry being distinct from the memory referenced by the memory reference;
• based at least in part on a content of the table entry, altering a manipulation of data or control transfer behavior of the architecturally-defined instruction in a manner incompatible with the architectural definition of the architecturally-defined instruction in the architecturally-defined instruction's native architecture.

A method, comprising the steps of:

• as part of the basic instruction cycle of executing an instruction of a non-supervisor mode program fetched for execution on a computer, consulting a table, entries of the table being indexed by addresses of instructions fetched, entries of the table containing attribute indicia of instructions whose addresses index to the respective entries;
• and
• controlling an architecturally-visible data manipulation behavior or control transfer behavior of the fetched instruction based at least in part on a content of a table entry indexed by the address of the fetched instruction, the table entries being architecturally-invisible in the fetched instruction's native architecture.