Decode and dispatch of multi-issue and multiple width instructions
AssigneesIntel Corporation, Analog Devices, Inc.
InventorsGregory A. Overkamp, Charles P. Roth, Ravi P. Singh
Life of this patent
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Abstract
In one particular embodiment, a processor receives and processes a plurality of instruction from a single instruction register. The processor loads the plurality of instructions into a single register and determines the number and size of instructions while the instructions are in the register. Each of the plurality of instructions is then simultaneously presented to the decoder. The decoder then decodes a first of the plurality of instructions and determines whether any additional instructions are present.
Claims18
A method, comprising:
- receiving instructions from a plurality of instruction sources into a first switching part receiving size information associated with the received instructions into a second switching part;
- using the first and second switching parts to switch among the instruction sources, said using simultaneously providing an instruction and associated size information at an output thereof;
- receiving the output from the first and second switching parts into a decoder;
- and
- using the decoder to decode each instruction, using said associated size information.
An apparatus comprising;
- a plurality of instruction sources generating instructions having varying instruction sizes;
- first and second switching elements, which respectively switch instructions originating with said instruction sources, and sizes of said instructions, so that both said instructions and said instruction sizes are simultaneously output;
- and
- a decoder, which receives said instructions and instruction sizes as inputs thereof.
A method comprising:
- producing instruction sizes respectively associated with a plurality of instructions originating from a plurality of instruction sources;
- switching instructions from said instruction sources using a first switching element;
- switching instruction sizes using a second switching element;
- and
- simultaneously outputting both of said instructions and said instruction sizes to a decoder.
An apparatus comprising:
- a first switching element to receive instructions from a plurality of instruction sources;
- a second switching element to receive size information associated with the received instructions, wherein the first and second switching elements are operable to switch among the plurality of instruction sources to simultaneously provide an instruction and associated size information at an output thereof;
- and
- a decoder to receive the output from the first and second switching elements and to decode each instruction using the associated size information.
Dependencies are inferred from the claim text.