Vector processing system
AssigneeBroadcom Corporation
InventorsStephen Barlow, Neil Bailey, Timothy Ramsdale, David Plowman, Robert Swann
Life of this patent
Estimating the term…
Abstract
A vector processing system for executing vector instructions, each instruction defining multiple value pairs, an operation to be executed and a modifier, the vector processing system comprising a plurality of parallel processing units, each arranged to receive one of said pairs of values and, when selected, to implement an operation on said value pair to generate a result, each processing unit comprising at least one flag and being selectable in dependence on a condition defined by said at least one flag, wherein the modifier defines the condition under which the parallel processing unit is individually selected.
Claims19
A vector processing system comprising:
- a circuit for receiving an instruction defining multiple value pairs, an operation to be executed and a modifier;
- a plurality of parallel processing units, each arranged to receive one of said value pairs and, when selected, to implement the operation on said value pair to generate a result, each processing unit in the plurality of parallel processing units comprising at least one flag and being selectable in dependence on a condition defined by said at least one flag and the modifier;
- and
- a scalar processing unit for receiving the results from more than one selected processing unit to generate a scalar result.
A method of vector processing, the method comprising:
- supplying to a first parallel processing unit a first pair of values on which an operation is to be implemented to generate a first result, wherein the first parallel processing unit is one of a plurality of parallel processing units;
- reading a modifier supplied with an instruction, the modifier defining a condition under which the first parallel processing unit is selected;
- comparing a state of at least one flag in the first parallel processing unit with the defined condition to determine whether or not the first parallel processing unit is selected;
- and
- if the first parallel processing unit is selected,
- executing the operation to generate the first result;
- supplying to a second parallel processing unit a second pair of values on which the operation is to be implemented to generate a second result, wherein the second parallel processing unit is another of the plurality of parallel processing units;
- reading the modifier supplied with the instruction, the modifier defining a condition under which the second parallel processing unit is selected;
- comparing a state of at least one flag in the second parallel processing unit with the defined condition to determine whether or not the second parallel processing unit is selected;
- and
- if the second parallel processing unit is selected,
- executing the operation to generate the second result, and processing the first result and the second result in a scalar result unit to produce a scalar result.
An integrated circuit for vector processing, wherein the integrated circuit comprises:
- a memory having stored thereon a computer program comprising an instruction stream including a vector instructions, the vector instruction defining
- multiple value pairs,
- an operation to be executed on each value pair, and
- a modifier;
- and
- a processor which comprises a plurality of parallel processing units, wherein each parallel processing unit is arranged to receive one of said value pairs and to selectively implement said operation, and wherein cooperation between the computer program and the processor being such that a parallel processing unit is selected to operate on the basis of a condition defined by at least one flag in the processor, and wherein the condition is set by the modifier in the vector instruction, and wherein more than one results from the plurality of parallel processing units is processed to generate a scalar result.
Dependencies are inferred from the claim text.