Page handling efficiency in a multithreaded processor
AssigneeIntel Corporation
InventorK S Venkatraman
Life of this patent
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Abstract
In a multithreaded processor, the efficiency of instruction processing may be improved by suspending an executing thread during the translation of a virtual memory address to a physical memory address when the address translation data must be retrieved from storage external to the processor. The suspension of an executing thread allows an address translation to be performed for an instruction in another thread while the address translation data needed for the first thread is retrieved.
Claims24
A page handling method for a multithreaded process, the method comprising:
- receiving a virtual memory address from an instruction in an executing thread at a multithreaded processor having a page miss handler and a processor memory that includes a first level of processor memory and a second level of processor memory,
- determining whether address translation data which associates a physical memory address with the received virtual memory address is stored in the first level of processor memory,
- when the address translation data is not stored in the first level of the processor memory, determining whether the address translation data is stored in the second level of processor memory, and
- when address translation data for the received virtual memory address is not stored in the first level of processor memory and is not stored in the second level of processor memory, suspending the executing thread and requesting retrieval from a storage location external to the processor of address translation data for the received virtual memory address.
A page-handling apparatus for a multithreaded process, the apparatus comprising:
- a multithreaded processor, including:
- a processor memory that includes a first level of processor memory and a second level of processor memory and is configured to store at least one association between a virtual memory address and a physical memory address, and
- a page miss handler configured to determine a physical memory address associated with a virtual memory address,
- wherein the multithreaded processor is configured to:
- receive a virtual memory address from an instruction in an executing thread,
- determine whether the address translation data which associates a physical memory address with the received virtual memory address is stored in the first level of processor memory,
- when the address translation data for the received virtual memory address is not stored in the first level of processor memory, determine whether the address translation data which associates a physical memory address with the received virtual memory address is stored in the second level of processor memory, and
- when the address translation data for the received virtual memory address is not stored in the first level processor memory and is not stored in the second level of processor memory, suspend the executing thread and request retrieval from a storage location external to the processor of address translation data for the received virtual memory address.
A computer-readable medium having embodied thereon a computer program configured to cause a processor to implement a page-handling technique, the computer program comprising code segments configured to cause a processor to:
- receive a virtual memory address from an instruction in an executing thread at a multithreaded processor having a page miss handler and a processor memory that includes a first level of processor memory and a second level of processor memory,
- determine whether address translation data which associates a physical memory address with the received virtual memory address is stored in the first level of processor memory,
- when address translation data for the received virtual memory address is not stored in the first level of processor memory, determine whether address translation data which associates a physical memory address with the received virtual memory address is stored in the second level of processor memory, and
- when address translation data for the received virtual memory address is not stored in the first level of processor memory and is not stored in the second level of processor memory, suspend the executing thread and request retrieval from a storage location external to the processor of address translation data for the received virtual memory address.
Dependencies are inferred from the claim text.