Mapper circuit with backup capability
AssigneeAdvanced Micro Devices, Inc.
InventorsBrian D. McMinn, Mitchell Alsup
Life of this patent
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Abstract
A mapper circuit with backup capability. In one embodiment, the mapper circuit may store associations between physical register names (PRNs) and logical register names (LRNs) in a plurality of storage locations, each of the storage locations corresponding to a speculative state. One of the storage locations may store a LRN-to-PRN mappings for a current speculative state, while the other storage locations may store LRN-to-PRN mappings for previous speculative states. In a case where the processor is required to back up (e.g., such as in the case of a branch misprediction), one of the mappings associated with a previous speculative state may be reverted to an association with the current speculative state.
Claims19
A mapper circuit for providing associations between logical registers and physical registers, the mapper circuit comprising a memory, the memory comprising:
- a plurality of addressable units, each addressable unit addressed by a different logical register name (LRN) to which that addressable unit is statically assigned, and each addressable unit including a plurality of storage locations, wherein a first storage location of the plurality of storage locations is configured to store a current physical register name (PRN) currently assigned to the LRN, and wherein each other storage location of the plurality of storage locations is configured to store an additional PRN previously assigned to the LRN;
- and
- a control circuit coupled to the plurality of addressable units, wherein the control circuit is configured, responsive to a new PRN being assigned to a first LRN that addresses a first addressable unit of the plurality of addressable units, to cause the current PRN in the first storage location of the first addressable unit to be copied to a second storage location which is one of the other storage locations of the first addressable unit, wherein the second storage location corresponds to a current checkpoint of a plurality of checkpoints.
A mapper circuit for providing associations between logical registers and physical registers, the mapper circuit comprising a memory, the memory comprising:
- a plurality of memory locations, each corresponding to a different physical register name (PRN), and wherein each memory location is configured to store a logical register name (LRN) and a plurality of valid indications, and wherein each of the valid indications corresponds to a checkpoint and is indicative of whether or not the PRN is assigned to the LRN at that checkpoint;
- wherein a portion of the memory location storing the LRN is implemented as a content addressable memory (CAM) for comparison with an input LRN to the mapper circuit, and wherein a first PRN corresponding to a first memory location of the plurality of memory locations is output as a mapping of the input LRN if the LRN in the first memory location matches the input LRN and a first valid indication of the plurality of valid indications that corresponds a current checkpoint indicates that the first PRN is assigned to that LRN at the current checkpoint.
Dependencies are inferred from the claim text.