Microprocessor with protection circuits to secure the access to its registers
AssigneeSTMicroelectronics S.r.l.
InventorFranck Roche
Life of this patent
Estimating the term…
Abstract
A microprocessor is provided with protection circuits to secure access to its registers. The microprocessor includes a plurality of protection circuits, each associated with a register of the microprocessor. The protection circuits automatically block selection of the registers after each resetting of the microprocessor. The releasing of a protection circuit associated with a register is done by the successive sending, on the data bus, of N passwords proper to the register during N first operations for the selection of the register with N≧1. The selection of the register is effective only for the subsequent operations for selection of the register up to the next resetting of the microprocessor.
Claims33
A microprocessor comprising:
- an address bus;
- a data bus;
- a plurality of read and write accessible registers connected to said data bus;
- an address decoder connected to said address bus for selecting said plurality of registers as a function of an address provided by said address bus;
- and
- a plurality of protection circuits connected between said address decoder and said plurality of registers, each protection circuit associated with a register to secure access thereto by blocking selection of said register after each resetting of the microprocessor, and releasing of said protection circuit by a successive sending on said data bus of N passwords proper to said register during N first operations for selection of said register with N≧1, the selection of said associated register being effective only for subsequent operations for the selection thereof until a next resetting of the microprocessor.
A microprocessor comprising:
- an address bus;
- a data bus;
- a plurality of read and write accessible registers connected to said data bus;
- an address decoder connected to said address bus for selecting said plurality of registers as a function of an address provided by said address bus;
- and
- a plurality of protection circuits connected between said address decoder and said plurality of registers, each protection circuit associated with a register to secure access thereto by blocking selection of said register during write access operations after each resetting of the microprocessor, and releasing of said protection circuit by a successive sending on said data bus of N passwords proper to said register during N first operations for selection of said register with N≧1, the selection of said associated register being effective only for subsequent operations for the selection thereof until a next resetting of the microprocessor.
A microprocessor comprising:
- an address bus;
- a data bus;
- a plurality of read and write accessible registers connected to said data bus;
- an address decoder connected to said address bus for selecting said plurality of registers as a function of an address provided by said address bus;
- and
- a plurality of protection circuits connected between said address decoder and said plurality of registers;
- each protection circuit associated with a register to secure access thereto by blocking selection of said register after each resetting of the microprocessor, at least two passwords are provided to each register, and releasing of said protection circuit by a successive sending on said data bus of at least 2N passwords proper to said register during N first operations for selection of said register with N≧1, the selection of said associated register being effective only for subsequent operations for the selection thereof until a next resetting of the microprocessor.
A method for securing access to a plurality of registers of a microprocessor, the method comprising the steps of:
- selecting one of said plurality of registers via an address decoder as a function of an address provided by an address bus connected to the address decoder;
- blocking selection of the plurality of registers via a plurality of protection circuits after each resetting of the microprocessor;
- and
- releasing a protection circuit associated with a selected register by successive sending on the data bus N passwords proper to the selected register during N first operations for selection of the register with N≧1, the selection of the register being effective only for subsequent operations for the selection thereof until a next resetting of the microprocessor.
Dependencies are inferred from the claim text.