Method and related apparatus for reordering access requests used to access main memory of a data processing system

A method of accessing a memory device of a computer system through a memory controller, the memory controller sequentially responding to a master device according to a sequence of access requests issued in order by the master device, the method comprising:

• (a) storing access requests generated from the master device in a request queue;
• (b) recording a plurality of latency values, the latency values respectively corresponding to the access requests stored in the request queue;
• (c) receiving a first access request and adding the first access request to the request queue with an associated queue priority according to latency values associated with the access requests already stored in the request queue and respectively adding a predetermined increment value to the latency values corresponding to access requests in the request queue having associated queue priorities that are lower than the queue priority of the first access request;
• and
• (d) sequentially accessing the memory device according to the associated queue priorities of the access requests stored in the request queue.

A memory controller for accessing a memory device of a computer system, the memory device being electrically connected to a memory controller, the memory controller sequentially responding to a master device according to a sequence of access requests issued in order by the master device, the memory controller comprising:

• a request queue for storing access requests generated from the master device;
• a latency monitoring unit electrically connected to the request queue for recording a plurality of latency values, the latency values respectively corresponding to the access requests stored in the request queue;
• and
• a reorder decision-making unit electrically connected to the request queue for controlling a first access request added to the request queue with an associated queue priority according to latency values associated with the access requests already stored in the request queue and respectively adding a predetermined increment value to the latency values corresponding to access requests in the request queue having associated queue priorities that are lower than the queue priority of the first access request;
• wherein the memory device is sequentially accessed according to the associated queue priorities of the access requests stored in the request queue.

A method for accessing a memory device of a computer system, the method comprising:

• receiving one or more access requests for accessing the memory device in a first predetermined order;
• identifying that the first and the second access requests access the same memory page;
• determining that a third access request is for accessing a different memory page;
• identifying a latency value associated with the third access request;
• examining whether the latency value associated with the third access request is increased to exceed a predetermined limit if the first access request is to be inserted;
• inserting the first access request between the second and the third access requests in the request queue;
• and
• increasing the latency value associated with the third access request by a predetermined incremental value.

A method for accessing a memory device of a computer system, the method comprising:

• receiving one or more access requests for accessing the memory device, the access requests accessing one or more memory pages;
• and
• identifying that a first access request received after a second access request accesses the same memory page as the second access request;
• determining that a third access request is for accessing a different memory page:
• identifying a latency value associated with the third access request;
• examining whether the latency value associated with the third access request is increased to exceed a predetermined limit if the first access request is to be inserted;
• inserting the first access request between the second and the third access requests in the request queue;
• and
• increasing the latency value associated with the third access request by a predetermined incremental value;
• and
• repeating the above identifying, determining and inserting steps for all received access requests.