Method for improved first level cache coherency
AssigneeUnisys Corporation
InventorPaul S. Neuman
Life of this patent
Estimating the term…
Abstract
A method of and apparatus for improving the efficiency of a data processing system employing a multiple level cache memory system. The efficiencies result from invalidating level one cache information based upon a level one cache memory write. Similarly, the invalidation can occur from system bus SNOOPs. In addition, level one and level two cache memory misses result in loading and recording of the requested data into both level one and level two cache memories. Furthermore, a level two cache memory parity error results in invalidation of the corresponding level one cache memory data.
Claims20
A data processing system comprising:
- a. a system bus;
- b. a processor with a system controller containing a semi-store-in level one cache memory having an associated duplicate tag memory responsively coupled to a dedicated level two cache memory having an associated tag memory which is responsively coupled via said system bus to a level three cache memory which is directly coupled to at least one memory storage unit;
- c. a circuit for directly SNOOPing said system bus;
- and
- d. First logic which invalidates a corresponding level one cache memory location in response to a non-local memory write request generated by another processor.
A data processing system comprising:
- a. A processor having a level one cache memory within a system controller;
- b. A level two cache memory located within said system controller dedicated to said processor and responsively coupled to said level one cache memory;
- c. a system bus;
- d. A memory storage unit;
- e. A level three cache memory responsively coupled to said level two cache memory via said system bus and responsively coupled to said memory storage unit;
- and
- f. A first circuit which invalidates a corresponding portion of said level one cache memory in response to a level one cache memory write hit and a level two cache memory hit.
A method of maintaining validity of data within a semi-store-in level one cache memory of a processor located within a system controller containing a duplicate tag memory and responsively coupled to a level two cache memory which is dedicated to said processor, which is located within said system controller having a tag memory, and which is responsively coupled to a system memory bus comprising:
- a. Formulating a write memory request within said processor;
- b. First checking for a level one cache memory hit in response to said write memory request;
- c. Second checking for a level two cache memory hit in response to a hit found by said first checking step;
- and
- d. Invalidating a portion of said level one cache memory corresponding to said write memory request in response to a hit found by said second checking step as indicated by said duplicate tag memory.
An apparatus comprising:
- a. executing means for executing program instructions;
- b. level one semi-store-in caching means located within a system controller and responsively coupled to said executing means for level one caching data;
- c. accessing means responsively coupled to said executing means and said level one semi-store-in caching means for accessing a data element from said level one semi-store-in means if said executing means requires accessing of said data element;
- d. level two caching means located within said system controller and responsively coupled to said requesting means for level two caching data and dedicated to said executing means;
- and
- e. first invalidating means responsively coupled to said level one semi-store-in caching means for invalidating said data element within said semi-store-in caching means if said data element is a write data element located within said level two caching means and within said semi-store-in level one caching means.
Dependencies are inferred from the claim text.