US 7,069,378 B2Granted

Multi-bank content addressable memory (CAM) devices having staged segment-to-segment soft and hard priority resolution circuits therein and methods of operating same

AssigneeIntegrated Device Technology, Inc.

InventorsKee Park, Scott Yu-Fan Chu

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Abstract

Content addressable memory (CAM) devices use both hard and soft priority techniques to allocate entries of different priority therein. The allocation of entries may change in response to additions or deletions of entries or as entries are reprioritized. The CAM devices include priority resolution circuits that can resolve competing soft and hard priorities between multiple hit signals that are generated in response to a search operation. Such hit signals may be active to reflect the presence of at least one matching entry within a CAM array block. The resolution of which active hit signal has the highest overall priority among many can be used to facilitate the identification of the location (e.g., array address and row address) of a highest priority matching entry within the entire CAM device. A priority resolution circuit may also resolve competing hard priorities between two or more active hit signals having equivalent soft priority.

Claims17

Dependent claims

A content addressable memory (CAM) device, comprising:

a first plurality of CAM array blocks configured to generate a first plurality of active hit signals in parallel in response to a search operation;
a second plurality of CAM array blocks configured to generate a second plurality of active hit signals in parallel in response to the search operation;
a first priority resolution circuit configured to resolve a first soft and hard priority competition between the first plurality of active hit signals;
and
a second priority resolution circuit configured to resolve a second soft and hard priority competition between the second plurality of active hit signals in a manner that relies on an outcome of the first soft and hard priority competition to identify whether any of the second plurality of active hit signals has a higher priority than a highest priority one of the first plurality of active hit signals;
wherein said first priority resolution circuit is responsive to a first plurality of soft priority signals and is configured to generate a first plurality of hierarchical control signals in response to the first soft and hard priority competition;
wherein said second priority resolution circuit is responsive to a second plurality of soft priority signals;
and
wherein at least some of the second plurality of soft priority signals are derived from the first plurality of hierarchical control signals.

6 more elements

Dependencies are inferred from the claim text.