Processor having systolic array pipeline for processing data packets

A processor for use in a router receiving data packets from a network, the router having a plurality of input ports and output ports, each data packet having a header and a body, the processor comprising:

• one or more input buffers for receiving data packets from the input ports of the router:
• a packet buffer for storing the body of each of the data packets;
• and a systolic array pipeline for processing the header of each of the data packets to determine to which output port the data packets should be routed,
• wherein said systolic array pipeline includes a first stage having a first functional unit, and a second stage having a second functional unit, wherein an output of the first functional unit from the first stage is coupled with an input of the second functional unit of the second stage.

A processor for use in a router receiving data packets from a network, the router having a plurality of input ports and output ports, each data packet having a header and a body, the processor comprising:

• one or more input buffers for receiving data packets from the input ports of the router;
• a packet buffer for storing the body of each of the data packets;
• and
• a systolic array pipeline for processing the header of each of the data packets to determine to which output port the data packets should be routed,
• wherein said systolic array pipeline includes a first stage having a plurality of functional units and a first register file, and a second stage having a plurality of functional units and a second register file, wherein outputs of the functional units from the first stage are coupled with inputs of the second register file of the second stage.

A processor for use in a router receiving data packets from a network, the router having a plurality of input ports and output ports, each data packet having a header and a body, the processor comprising:

• one or more input buffers for receiving data packets from the input ports of the router;
• a packet buffer for storing the body of each of the data packets;
• and
• a systolic array pipeline for processing the header of each of the data packets to determine to which output port the data packets should be routed,
• wherein said systolic array pipeline includes a control to recirculate data corresponding to the packet within the systolic array pipeline, thereby providing within the processor additional processing of the data corresponding to the packet within the processor.

A processor for use in a router receiving data packets from a network, the router having a plurality of input ports and output ports, each data packet having a header and a body, the processor comprising:

• one or more input buffers for receiving data packets from the input ports of the router;
• a packet buffer for storing the body of each of the data packets;
• and
• a systolic array pipeline for processing the header of each of the data packets to determine to which output port the data packets should be routed,
• wherein said systolic array pipeline includes a parsing execution unit for extracting data from the packet to form a packet context.

A processor for use in a router receiving data packets from a network, the router having a plurality of input ports and output ports, each data packet having a header and a body, the processor comprising:

• one or more input buffers for receiving data packets from the input ports of the router;
• a packet buffer for storing the body of each of the data packets;
• and
• a systolic array pipeline for processing the header of each of the data packets to determine to which output port the data packets should be routed,
• wherein the systolic array pipeline is divided into multiple execution units, each execution unit having one or more stages, and data corresponding to the packet is passed through one of the execution units of the systolic array pipeline more than once for processing within the execution unit.