On-chip bus
AssigneeLSI Logic Corporation
InventorFrank Worrell
Life of this patent
Estimating the term…
Abstract
A bus that may be used in an integrated circuit chip. The bus generally comprises a master interface, a slave interface, and a control logic. The master interface may be configured to (i) receive an early command signal having a predetermined timing relationship to a first clock edge and (ii) present a bus wait signal proximate a second clock edge. The slave interface may be configured to (i) present a command signal a delay after the first clock edge and (ii) receive a slave wait signal. The control logic may be configured to (i) register the early command signal to generate the command signal and (ii) convert the slave wait signal into the bus wait signal.
Claims20
A bus comprising:
- a master interface connectable to a master device external to said bus and configured to (i) receive an early command signal from said master device with an early timing relationship to a first clock edge of a system clock and (ii) present a bus wait signal to said master device, wherein said early timing relationship comprises validity both a set-up time before and a hold-time after a respective edge of said system clock;
- a slave interface connectable to a slave device external to said bus and configured to (i) present a command signal to said slave device with a standard timing relationship to said first clock edge, (ii) present said early command signal to said slave device with said early timing relationship to said first clock edge and (iii) receive a slave wait signal from said slave device, wherein said standard timing relationship comprises a delay after said respective clock edge;
- and
- a control logic configured to (i) register said early command signal with said first clock edge to generate said command signal, (ii) multiplex said early command signal to said slave interface and (iii) multiplex said slave wait signal into said bus wait signal.
A method for operating a bus connectable to a master device and a slave device both external to said bus, comprising the steps of:
- (A) receiving an early command signal with an early timing relationship to a first clock edge of a system clock at a master interface of said bus from said master device, wherein said early timing relationship comprises validity both a set-up time before and a hold-time after a respective edge of said system clock;
- (B) registering said early command signal with said first clock edge to generate a command signal;
- (C) presenting said command signal with a standard timing relationship to said first clock edge at a slave interface of said bus to said slave device, wherein said standard timing relationship comprises validity a delay after said respective clock edge;
- (D) multiplexing said early command signal to said slave interface;
- (E) receiving a slave wait signal at said slave interface from said slave device;
- (F) multiplexing said slave wait signal into a bus wait signal;
- and
- (G) presenting said bus wait signal at said master interface to said master device.
A bus connectable to a master device and a slave device both external to said bus, comprising:
- means for receiving an early command signal with an early timing relationship to a first clock edge of a system clock at a master interface from said master device, wherein said early timing relationship comprises validity both a set-up time before and a hold-time after a respective edge of said system clock;
- means for registering said early command signal with said first clock edge to generate a command signal;
- means for presenting said command signal with a standard timing relationship to said first clock edge at a slave interface to said slave device, wherein said standard timing relationship comprises validity a delay after said respective clock edge;
- means for receiving a slave wait signal at said slave interface from said slave device;
- means for multiplexing said slave wait signal into a bus wait signal;
- and
- means for presenting said bus wait signal at said master interface to said master device.
Dependencies are inferred from the claim text.