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US 7,069,362 B2Granted
Topology for shared memory computer system
AssigneeInternational Business Machines Corporation
InventorsMichael A. Blake, Pak-kin Mak
Life of this patent
Estimating the term…
Abstract
A dual ring topology for multiprocessing computer systems. The dual ring topology interconnects multiple building blocks (nodes) to each other, each node comprising processing elements, memory and IO devices. The topology allows for the dual rings to be temporarily transformed into a single ring structure while a node is added, repaired or replaced while the rest of the system continues to operate thereby allowing the remaining nodes in the system to remain fully connected to one another.
Claims10
A processing system, comprising:
- a first ring and a second ring for interconnecting a plurality of nodes, each of said plurality of nodes comprising:
- at least one processor;
- memory;
- an input bus for said first ring;
- an input bus for said second ring;
- an output bus for said first ring;
- an output bus for said second ring;
- and
- a device for coupling said input bus of said first ring to said output bus of said second ring or said input bus of said second ring to said output bus of said first ring;
- wherein said coupling provides interprocessor communication among at least two of said plurality of nodes by allowing data of said first ring to reach said second ring;
- wherein data in said first ring flows in opposite directions with respect to said second ring;
- wherein each of said plurality of nodes further comprises hardware for broadcasting snoop addresses on said first ring and said second ring simultaneously;
- wherein each of said plurality of nodes further comprises hardware for forwarding an incoming snoop addresses on the same ring that said incoming snoop address was received on;
- wherein each of said plurality of nodes further comprises an address bus availability model to determine when a snoop addresses can be broadcast to one of said plurality of nodes that has not received said snoop address being broadcast.
11 more elements
A processing system, comprising:
- a first ring and a second ring for interconnecting a plurality of nodes, each of said plurality of nodes comprising:
- at least one processor;
- memory;
- an input bus for said first ring;
- an input bus for said second ring;
- an output bus for said first ring;
- am output bus for said second ring;
- and
- a device for coupling said input bus of said first ring to said output bus of said second ring or said input bus of said second ring to said output bus of said first ring,
- wherein said coupling provides interprocessor communication among at least two of said plurality of nodes by allowing data of said first ring to reach said second ring;
- wherein data in said first ring flows in opposite directions with respect to said second ring;
- wherein each of said plurality of nodes further comprises hardware for broadcasting snoop addresses on said first ring and said second ring simultaneously;
- wherein each of said plurality of nodes further comprises hardware for forwarding an incoming snoop addresses on tho same ring that said incoming snoop address was received on;
- wherein each of said plurality of nodes further comprises a data availability model to determine when data can be broadcast to one of said plurality of nodes on the same ring said data is received.
11 more elements
A processing system, comprising:
- a first ring and a second ring interconnecting a plurality of nodes, each of said plurality of nodes comprising:
- at least one processor;
- memory;
- an input bus for said first ring;
- an input bus for said second ring;
- an output bus for said first ring;
- an output bus for said second ring;
- and
- a device for coupling said input bus of said first ring to said output bus of said second ring or said input bus of said second ring to said output bus of said first ring,
- wherein said coupling provides interprocessor communication among at least two of said plurality of nodes allowing data of said first ring to reach said second ring;
- wherein data in said first ring flows in opposite directions with respect to said second ring;
- further comprising means for accumulating an incoming ring early response and a local on-node early response on each of said plurality of nodes prior to broadcasting said early response on either said first ring or said second ring.
9 more elements
A processing system, comprising:
- a first ring end a second ring for interconnecting a plurality of nodes, each of said plurality of nodes comprising;
- at least one processor;
- memory;
- an input bus for said first ring;
- an input bus for said second ring;
- an output bus for said first ring;
- an output bus for said second ring;
- and
- a device for coupling said input bus of said first ring to said output bus of said second ring or said input bus of said second ring to said output bus of said first ring,
- wherein said coupling provides interprocessor communication among at least two of said plurality of nodes by allowing data of said first ring to reach said second ring;
- wherein data in said first ring flows in opposite directions with respect to said second ring;
- further comprising means for using an early response availability model on each of said plurality of nodes to determine when early responses can be broadcast on either said first ring or said second ring.
9 more elements
A processing system, comprising:
- a first ring and a second ring for interconnecting a plurality of nodes, each of said plurality of nodes comprising:
- at least one processor;
- memory;
- an input bus for said first ring;
- an input bus for said second ring;
- an output bus for said first ring;
- an output bus for said second ring;
- and
- a device for coupling said input bus of said first ring to said output bus of said second ring or said input bus of said second ring to said output bus of said first ring,
- wherein said coupling provides interprocessor communication among at least two of said plurality of nodes by allowing data of said first ring to reach said second ring;
- wherein data in said first ring flows in opposite directions with respect to said second ring
- further comprising means for accumulating an incoming ring final response, a local on-node final response, and an outgoing early response on each of said plurality of nodes prior to broadcasting said final response on either said first ring or said second ring.
9 more elements
A processing system, comprising:
- a first ring and a second ring for interconnecting a plurality of nodes, each of said plurality of nodes comprising:
- at least one processor;
- memory;
- an input bus for said first ring;
- an input bus for said second ring;
- an output bus for said first ring;
- an output bus for said second ring;
- and
- a device for coupling said input bus of said first ring to said output bus of said second ring or said input bus of said second ring to said output bus of said first ring,
- wherein said coupling provides interprocessor communication among at least two of said plurality of nodes by allowing data of said first ring to reach said second ring;
- wherein data in said first ring flows in opposite directions with respect to said second ring;
- further comprising means for using a final response availability model on each of said plurality of nodes to determine when final responses can be broadcast on either said first ring or said second ring.
9 more elements
A processing system, comprising:
- a first ring and a second ring for interconnecting a plurality of nodes, each of said plurality of nodes comprising:
- at least one processor;
- memory;
- an input bus for said first ring;
- an input bus for said second ring;
- an output bus for said first ring;
- an output bus for said second ring;
- and
- a device for coupling said input bus of said first ring to said output bus of said second ring or said input bus of said second ring to said output bus of said first ring,
- wherein said coupling provides interprocessor communication among at least two of said plurality of nodes by allowing data of said first ring to reach said second ring;
- wherein data in said first ring flows in opposite directions with respect to said second ring;
- further comprises means for selecting either said first ring or said second ring when moving data from a source node of said plurality of nodes to a target node of said plurality of nodes, wherein the selecting is based upon the proximity of said source node and said target node on said first ring and said second ring.
9 more elements
A processing system, comprising:
- a first ring and a second ring for interconnecting a plurality of nodes, each of said plurality of nodes comprising:
- at least one processor;
- memory;
- an input bus for said first ring;
- an input bus for said second ring;
- an output bus for said first ring;
- an output bus for said second ring;
- and
- a device for coupling said input bus of said first ring to said output bus of said second ring or said input bus of said second ring to said output bus of said first ring,
- wherein said coupling provides interprocessor communication among at least two of said plurality of nodes by allowing data of said first ring to reach said second ring;
- wherein data in said first ring flows in opposite directions with respect to said second ring;
- further comprising means for using an address-based scheme for selecting either said first ring or said second ring when moving data from a source node of said plurality of nodes to a target node of said plurality of nodes when said source node is equidistant on each of said first ring or said second ring.
9 more elements
Dependencies are inferred from the claim text.