Method and apparatus for detecting a device's ability to run at a selected frequency in a PCI non-inhibit bus-connect mode
AssigneeIntel Corporation
InventorsClark S. Thurlo, Lorenza L. Hawthorne, III
Life of this patent
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Abstract
Embodiments of the present invention detect a device's ability to run at a particular frequency on a PCI bus operating in a non-inhibit bus mode. In one embodiment, expansion slots are powered on, connected to the PCI bus and reset. The expansion slots are then disconnected from the PCI bus while power is applied. A frequency detection algorithm, which is operable regardless of the inhibit bus connect setting or capability, is executed. The expansion slots are then reconnected to the PCI bus.
Claims29
A method of detecting the frequency of one or more devices connected to expansion slots associated with a Peripheral Component Interconnect (PCI) bus, comprising:
- powering on the expansion slots;
- connecting the expansion slots to the PCI bus;
- disconnecting the expansion slots from the PCI bus while power is applied to the expansion slots;
- detecting the speed of operation each device connected to one of the expansion slots;
- and
- reconnecting the expansion slots to the PCI bus.
A machine-readable medium having stored therein a plurality of machine-readable instructions executable by a processor to detect the frequency of one or more devices connected to expansion slots associated with a Peripheral Component Interconnect (PCI) bus, comprising:
- instructions to power on the expansion slots;
- instructions to connect the expansion slots to the PCI bus instructions to disconnect the expansion slots from the PCI bus while power is applied to the expansion slots;
- instructions to detect the speed of operation each device connected to one of the expansion slots;
- and
- instructions to reconnect the expansion slots to the PCI bus.
A computer system, comprising:
- a host processor coupled to a host bus;
- a bridge controller coupled to the host bus;
- and
- a bus system that is hot plug connectable to the bridge controller, the bus system comprising:
- one or more buses coupled to the bus bridge, each bus including one or more expansion slots for receiving a device, wherein the controller powers on the expansion slots, disconnects the expansion slots from the bus while power is applied to the expansion slots, and detect the speed of operation each device connected to one of the expansion slots in a non-inhibit bus connect mode.
A system, comprising:
- a bridge controller coupled to a host bus for receiving signals from a processor;
- and
- a bus system that is connectable to the bridge controller, the bus system comprising:
- one or more Peripheral Component Interconnect (PCI) buses coupled to the bus bridge, each bus including one or more expansion slots for receiving a device, wherein the controller powers on the expansion slots, disconnects the expansion slots from the bus while power is applied to the expansion slots to detect the speed of operation each device connected to one of the expansion slots in a non-inhibit bus connect mode.
Dependencies are inferred from the claim text.