Circuit and technique to stall the communication of data over a double pumped bus

A computer system comprising:

• a system memory;
• and
• a processor coupled to system memory, the processor including:
• a wire;
• a first circuit to receive indications of first data associated with a first data set and second data associated with a second data set;
• and
• a second circuit coupled to the first circuit to cause the first circuit to:
• in a first mode, communicate indications of the first data to the wire in synchronization with a first phase of a clock signal and communicate indications of the second data to the wire in synchronization with a second phase of the clock signal, and
• in a second mode, communicate the indications of the first data to the wire in synchronization with the first phase and prevent communication of the second data during the second phase.

A method comprising:

• receiving first indications of first data associated with a first data set;
• receiving second indications of second data associated with a second data set;
• in a first mode, communicating the first indications to a double pumped bus in synchronization with a first phase of a clock signal and communicating the second indications to the double pumped bus in synchronization with a second phase of the clock signal;
• and
• in a second mode, communicating the first indications to the double pumped bus in synchronization with the first phase and preventing communication of the second indications to the double pumped bus during the second phase.