Providing shared and non-shared access to memory in a system with plural processor coherence domains

A method for managing memory in a multiprocessor system, comprising:

• defining a plurality of processor coherence domains within a system coherence domain of a multiprocessor system, the processor coherence domains each including a plurality of processors and a processor memory;
• providing shared access to data in the processor memory of each processor coherence domain only to elements of the multiprocessor system within the processor coherence domain;
• and
• providing non-shared access to data in the processor memory of each processor coherence domain to elements of the multiprocessor system within and outside of the processor coherence domain;
• providing a limited sharing vector for each processor memory, the limited sharing vector operable to identify only a portion of processors in the multiprocessor system.

A method for managing memory in a multiprocessor system, comprising:

• defining a plurality of processor coherence domains within a system coherence domain of a multiprocessor system, the processor coherence domains each including a plurality of processors and a processor memory;
• providing shared access to data in the processor memory of each processor coherence domain only to elements of the multiprocessor system within the processor coherence domain;
• and
• providing non-shared access to data in the processor memory of each processor coherence domain to elements of the multiprocessor system within and outside of the processor coherence domain;
• determining whether an element requesting shared access to a processor memory is outside of the processor coherence domain of the processor memory;
• and
• denying shared access if the element is outside of the processor coherence domain.

A multiprocessor system for managing memory among a plurality of processors, comprising:

• a system coherence domain;
• plurality of processor coherence domains defined within the system coherence domain;
• wherein the processor coherence domains each include a plurality of processors and a processor memory;
• wherein the processor coherence domains are each operable to provide shared access to data in their processor memory only to elements of the multiprocessor system within the processor coherence domain and operable to provide non-shared access to data in their processor memory to elements within and outside of the processor coherence domain;
• a plurality of partition coherence domains within the system coherence domain of the multiprocessor system, each partition coherence domain including at least one processor coherence domain, a router node, and a peer input/output node, each partition coherence domain providing memory coherence for its respective processor coherence domain, router node, and peer input/output node.

A multiprocessor system for managing memory among a plurality of processors, comprising:

• a system coherence domain;
• plurality of processor coherence domains defined within the system coherence domain;
• wherein the processor coherence domains each include a plurality of processors and a processor memory;
• and
• wherein the processor coherence domains are each operable to provide shared access to data in their processor memory only to elements of the multiprocessor system within the processor coherence domain and operable to provide non-shared access to data in their processor memory to elements within and outside of the processor coherence domain;
• each processor memory further comprising:
• a limited sharing vector for each data piece within the processor memory;
• and
• the limited sharing vector operable to identity only a portion of processors in the multiprocessor system.

A multiprocessor system for managing memory among a plurality of processors, comprising:

• a system coherence domain;
• plurality of processor coherence domains defined within the system coherence domain;
• wherein the processor coherence domains each include a plurality of processors and a processor memory;
• and
• wherein the processor coherence domains are each operable to provide shared access to data in their processor memory only to elements of the multiprocessor system within the processor coherence domain and operable to provide non-shared access to data in their processor memory to elements within and outside of the processor coherence domain;
• each processor memory operable to determine whether an element requesting shared access is outside of the processor coherence domain of the processor memory and to deny shared access if the element is outside of the processor coherence domain.

A method for managing processor memory in a scalable processor system, comprising:

• receiving a request from an element for shared access to data in a processor memory;
• determining whether the element is outside of a processor coherence domain of the processor memory;
• and
• denying the request for shared access if the element is outside of the processor coherence domain of the processor memory;
• granting non-shared access to an element regardless of whether the element is within or outside of the processor coherence domain of the processor memory.