US 7,069,178 B2 · Method of predicting quiescent current variation of an integrated circuit die from a process monitor derating factor

Abstract

In exemplary embodiments, a method and computer program product for predicting quiescent current variation of an integrated circuit die include steps of: (a) receiving as input a value of a derating factor from a process monitor cell on an integrated circuit die and an on-chip variation of the derating factor; (b) constructing a curve fitting formula for estimating a quiescent current of the integrated circuit die as a function of the derating factor; (c) calculating minimum and maximum values of the quiescent current from the curve fitting formula, the value of the derating factor from the process monitor cell, and the on-chip variation of the derating factor to generate an estimate of minimum and maximum values for the quiescent current; and (d) generating as output the estimated minimum and maximum values of the quiescent current.

Claims23

Dependent claims

A method comprising steps of:

(a) receiving as input a value of a aerating factor from a process monitor cell on an integrated circuit die and an on-chip variation of the derating factor;
(b) constructing a curve fitting formula for estimating a quiescent current of the integrated circuit die as a function of the derating factor;
(c) calculating minimum and maximum values of the quiescent current from the curve fitting formula, the value of the derating factor, and the on-chip variation of the derating factor to generate an estimate of minimum and maximum values of the quiescent current;
and
(d) generating as output the estimated minimum and maximum values of the quiescent current.

2 more elements

A computer program product comprising:

a medium for embodying a computer program for input to a computer;
and
a computer program embodied in the medium for causing the computer to perform steps of:
(a) receiving as input an integrated circuit design, values of quiescent current of each cell in the integrated circuit design for multiple process corners of a derating factor, a value of the derating factor from a process monitor cell, and an onchip variation of the derating factor;
(b) generating a design statistic file that includes a name and quantity of each cell in the integrated circuit design;
(c) constructing a curve fitting formula for the quiescent current of each cell named in the design statistic file as a function of the derating factor;
(d) calculating a minimum and a maximum value of the quiescent current for each cell named in the design statistic file from the curve fitting formula, from the value of the derating factor, and from the on-chip variation of the derating factor;
(e) multiplying the minimum and maximum values of quiescent current calculated for each cell named in the design statistic file by a corresponding quantity of the cell in the design statistic file to generate a minimum product and a maximum product respectively for the cell;
(f) summing the minimum product of each cell to generate an estimated minimum quiescent current of the integrated circuit design;
(g) summing the maximmn product of each cell to generate an estimated maximum quiescent current of the integrated circuit design;
and
(h) generating as output the estimated minimum and maximum values of quiescent current of the integrated circuit design as a function of the derating factor.

9 more elements

Dependencies are inferred from the claim text.

Method of predicting quiescent current variation of an integrated circuit die from a process monitor derating factor

Life of this patent

Method of predicting quiescent current variation of an integrated circuit die from a process monitor derating factor

Life of this patent

Abstract

Claims23