Current cell type digital-to-analog converter
AssigneeOki Electric Industry Co., Ltd.
InventorMasaru Sekiguchi
Life of this patent
Estimating the term…
Abstract
The current cell matrix includes 63 upper current cells and one lower current cell. Each of the current cells has 4 constant current transistors having the same size with respect to each other. The upper current cell outputs drain currents of all the constant current transistors when the cell is selected by the upper decoder. The lower current cell outputs drain currents of none, one or two constant current transistors in accordance with the select signal from the lower decoder. The analog output terminal combines and outputs the currents of the selected constant current cells. The current cell type digital-to-analog converter has the decreased differential linearity error and the decreased integral linearity error.
Claims20
A current cell type digital-to-analog converter comprising:
- a current cell matrix including a plurality of upper current cells and at least one lower current cell so as to form a matrix pattern, in which all of the current cells have the same number of constant current transistors connected in parallel, and the constant current transistors are the same size;
- an upper control circuit provided within each of the upper current cells for outputting currents of all the constant current transistors within the upper current cell when the upper current cell is selected;
- at least one lower control circuit provided within each of the at least one lower current cell for outputting only current of a predetermined number of constant current transistors within the lower current cell when the lower current cell is selected;
- a plurality of power supply lines respectively provided in rows of the current cell matrix so that each power supply line supplies currents to the constant current transistors provided in the upper current cell and the lower current cell provided in the corresponding row;
- an upper decoder for selecting none or at least one of the upper control circuits in accordance with predetermined one or more upper bits of a digital value;
- a lower decoder for selecting none or at least one of the lower control circuits in accordance with predetermined one or more lower bits of the digital value;
- and
- an analog output terminal for outputting a summation of output currents of the upper current cells and the at least one lower current cell.
A current cell type digital-to-analog converter comprising:
- matrix means including a plurality of upper current cells and at least one lower current cell so as to form a matrix pattern, in which all of the current cells have the same number of constant current transistors connected in parallel, and the constant current transistors are the same size;
- first means provided within each of the upper current cells for outputting currents of all the constant current transistors within the upper current cell when the upper current cell is selected;
- at least one second means provided within each of the at least one lower current cell for outputting only current of a predetermined number of constant current transistors within the lower current cell when the lower current cell is selected;
- a plurality of third means respectively provided in rows of the matrix means so that each third means supplies currents to the constant current transistors provided in the upper current cell and the lower current cell provided in the corresponding row;
- fourth means for selecting none or at least one of the first means in accordance with predetermined one or more upper bits of a digital value;
- fifth means for selecting none or at least one of the second means in accordance with predetermined one or more lower bits of the digital value;
- and
- sixth means for outputting a summation of output currents of the upper current cells and the at least one lower current cell.
Dependencies are inferred from the claim text.