Data encryption for suppression of data-related in-band harmonics in digital to analog converters

A method of n-bit digital-to-analog converter chip parallel input data encryption and decryption wherein said encryption occurs off said DAC chip such that data-related in-band harmonics are suppressed, comprising the steps of:

• a. loading an n-bit raw data word into a first array of latches located off a DAC chip, said first array of latches comprised of a plurality of D-Type flip flop devices each having a data input, a clock input, and an outputs,
• b. loading an n-bit pseudo random data word into a first multi-stage shift register located off said DAC chip, said first multi-stage shift register comprised of a plurality of D-Type flip flop devices each having a data input, a clock input, and first and second outputs, said plurality of D-Type flip flop devices being coupled in series by having said first output of a preceding device coupled to said data input of a following device,
• c. clocking said first array of latches and said first multi-stage shift register to generate outputs of said first array of latches and first and second outputs of said first multi-stage shift register;
• d. transferring said outputs of said first array of latches and said second outputs of said first multi-stage shift register into a first array of exclusive-OR logic gates located off said DAC chip, said first array of exclusive-OR logic gates comprised of a plurality of exclusive-OR logic gates each having first and second inputs, and an output;
• e. said first array of exclusive-OR logic gates performing an exclusive-OR logic examination of said outputs of said first array of latches and said second outputs of said first multi-stage shift register, said examination resulting in a first exclusive-OR logic gate array output, said first exclusive-OR logic gate array output being an n-bit encrypted data word;
• f. loading said n-bit encrypted data word into a second array of latches located on said DAC chip, said second array of latches comprised of a plurality of D-Type flip flop devices each having a data input, a clock input, and an outputs;
• g. loading said n-bit pseudo random data word into a second multi-stage shift register located on said DAC chip, said second multi-stage shift register comprised of a plurality of D-Type flip flop devices each having a data input, a clock input, and first and second outputs;
• wherein said plurality of D-Type flip flop devices is coupled in series by having said first output of a D-Type flip flop coupled to said data input of an adjacent D-Type flip flop,
• h. clocking said second array of latches and said second multi-stage shift register to generate outputs of said second array of latches and first and second outputs of said second multi-stage shift register;
• i. transferring said outputs of said second array of latches and said second outputs of said second multi-stage shift register into a second array of exclusive-OR logic gates located on said DAC chip, said second array of exclusive-OR logic gates comprised of a plurality of exclusive-OR logic gates each having first and second inputs, and an output;
• and
• j. said second array of exclusive-OR logic gates performing an exclusive-OR logic examination of said first outputs of said second array of latches and said second outputs of said second multi-stage shift register, said examination resulting in a second exclusive-OR logic gate array output, said second exclusive-OR logic gate array output being said n-bit raw data word.